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| www.fairchildsemi.com rev. 1.0.3 1/24/05 general description the fms7401l is a digital power controller designed for applications requiring ease of digital based control over ana- log based implementations. the fms7401l is an ideal solu- tion to implement ballast control, motor control and battery management functions. it integrates a wide variety of analog blocks with an 8-bit microcontroller core to offer a comple- mentary feature set with high performance, low power and small size in a single chip. the fms7401l is intended for applications using a supply v oltage in the 2.7v to 3.6v range. it is fabricated using cmos technology and is fully static offering a signi?ant power savings. the fms7401l is available in both 8-pin and 14-pin pdip, soic and tssop packages. features 8-bit microcontroller core 1k bytes on-board code eeprom 64 bytes data eeprom 64 bytes sram ? atchdog reset multi-input wakeup on all general purpose i/o pins ? ast 12-bit pwm timer with dead time control and half- bridge output drive ?input capture mode 5-ch 8-bit analog-to-digital converter ?20 ? conversion time ?sample and hold ?internal voltage reference (1.21v) ?gated auto-sampling mode auto-zero ampli?r (gain 16) uncommitted ampli?r internal current source generator (1ma) on-chip oscillator ?no external components ?1? instruction cycle time on-chip power-on reset programmable read and write disable functions memory mapped i/o programmable comparator (63 levels) brown-out reset software selectable i/o option push-pull outputs with tri-state option ? eak pull-up or high impedance inputs fully static cmos ?power saving halt mode ?< 1.3? @ 3.3v ?power saving idle mode ?< 180? @ 3.3v single supply operation ?2.7v ?3.6v 40 years data retention 100,000 data changes 8-/14-pin pdip, soic, and tssop packages in-circuit programming ?fast page-write programming mode fms7401l digital power controller device supply voltage program memory (bytes) data memory (bytes) i/o pin count sram data eeprom fms7401l 2.7v ?3.6v 1k 64 64 6 8 fms7401l 2.7v ?3.6v 1k 64 64 8 14
fms7401l 2 rev. 1.0.3 1/24/05 block diagram figure 1. fms7401l block and connection diagram pin con?urations analog mux 8-bit adc progr. reference digital filter internal oscillator power-on reset and brown-out reset 8-bit microcontroller core 1024 bytes code eeprom memory 64 bytes sram 64bytes data eeprom memory timer 0 and watchdog pwm timer 1 and dead time control i/o ports g3/ain1 g2/ain2 g4/ain0 vcc gnd g0/t1hs1 g5/t1hs2 s/h + _ nc/gnd x16 autozero amplifier unit gain + _ a out v ref vcc uncommitted amplifier + _ sr_gnd ach5 reset g1/ain3/ adstrobe a out g7/ain4/ a out g6/-a in programmable comparator ach2 ach3 ach4 ach1 y g4/ain0 g3/ain1 g1/ain3 g2/ain2 g5/t1hs2 gnd vcc g0/t1hs1 1 2 6 7 8 3 4 5 g5/t1hs2 g2/ain2 gnd g4/ain0 g3/ain1 vcc g0/t1hs1 g1/ain3 1 2 6 7 8 3 4 5 fms7401l 8-pin pdip/soic fms7401l 8-pin tssop fms7401l 14-pin pdip/soic/tssop g4/ain0 g3/ain1 g1/ain3 g2/ain2 g5/t1hs2 gnd reset sr_gnd nc/gnd g0/t1hs1 nc/vcc vcc 1 2 6 78 9 13 14 3 411 12 510 g7/a out g6/-a in product specification fms7401l rev. 1.0.3 1/24/05 3 fms7401l pin de?itions pin number pin name pin function description 8-pin 14-pin pdip soic tssop pdip soic tssop 13 1 g4/ain0 general purpose i/o port (bit 4 of the i/o configuration registers). ain0 analog input of the adc (autozero amplifier? positive terminal). programmable comparator non-inverting input, if compsel=0. 24 3 gnd digital ground pin. 35 6 g2/ain2 general purpose i/o port (bit 2 of the i/o configuration registers). ain2 analog input of the adc. programmable comparator non-inverting input, if compsel=1. 46 7 g1/ain3/ adstrobe general purpose i/o port (bit 1 of the i/o configuration registers). ain3 analog input of the adc. external digital clock input. pwm timer 1? adstrobe output. 57 9 g3/ain1 general purpose i/o port (bit 3 of the i/o configuration registers). ain1 analog input of the adc. internal current source generator pin. 6810 g0/ t1hs1 general purpose i/o port (bit 0 of the i/o configuration registers). pwm timer 1? t1hs1 output. 7112 g5/ t1hs2 general purpose i/o port (bit 5 of the i/o configuration registers). pwm timer 1? t1hs2 output. 82 14 vcc supply voltage input. 2 sr_gnd ain0 analog input of the adc (autozero amplifier? negative terminal). sr_gnd is internally connected to gnd in the 8-pin fms7401l. 4 g6/-a in general purpose i/o port (bit 6 of the i/o configuration registers). uncommitted amplifier negative analog input. 5 g7/ain4/ a out general purpose i/o port (bit 7 of the i/o configuration registers). ain4 analog input of the adc. uncommitted amplifier analog output. 8 nc/gnd in the fms7401l, pin 8 is internally connected to gnd. externally, pin 8 should be left unconnected or connected to gnd. 11 reset active low external reset input. 13 nc/vcc in the fms7401l, vcc is internally connected to pin 13. externally, pin 13 should either be left unconnected or connected to pin 13. fms7401l product specification 4 rev. 1.0.3 1/24/05 ta b le of contents fms7401l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 pin con gurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 fms7401l pin de nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 reset cir cuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 po wer -on reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 bro wn-out reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 clock cir cuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 p o wer sa ving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1.1 pll steps for halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.1 pll steps for idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 adc cir cuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 adc circuit con guration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1.1 adcntrl1 re gister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.2 adcntrl2 re gister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 adc con v ersion modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.1 analog input v oltage and its 8-bit digital result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2.2 adc gated auto-sampling mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2.3 adc con v ersion clock con guration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3 autozero ampli er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4 uncommitted ampli er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.5 current source generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 pr ogrammable comparator cir cuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 programmable comparator s v oltage threshold le v els (vloop=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 hardw are v oltage and current loop control (vloop=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3 digital delay filter with pwmoff output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 pwm t imer 1 cir cuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1 pwm t imer 1 con guration re gisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1.1 pscale re gister and t imer 1 clock con guration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1.2 pwm cycle con guration re gisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1.3 t imer 1 control re gister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2 pulse w idth modulation (pwm) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.3 input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7 t imer 0 cir cuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.1 idle t imer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.2 w atchdog t imer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8 i/o p orts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.1 i/o re gisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9 multi-input w ak eup cir cuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.1 miw con guration re gisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 product specification fms7401l rev. 1.0.3 1/24/05 5 10 8-bit micr ocontr oller cor e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.1 core re gisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.1.1 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1.2 x-pointer (x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1.3 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1.4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1.5 status re gister (sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1.6 interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.2 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11 de vice memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1 initialization re gisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.2 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12 in-cir cuit pr ogramming speci cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.1 programming mode interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.2 programming protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12.2.1 byte write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12.2.2 p age write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12.2.3 byte read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.2.4 program memory erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 13 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 13.1 fms7401l (2.7v to 3.6v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 ordering inf ormation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 ph ysical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 fms7401l product specification 6 rev. 1.0.3 1/24/05 list of figures figure 1. fms7401l block and connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 2. bor and por circuit relationship diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. internal clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. external clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. recommended halt/idle flo w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 6. adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. current generator interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 8. programmable comparator block diagram (vloop = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 9. programmable comparator block diagram (vloop = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 10. digital delay t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 11. t imer 1 s pwm mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 12. example pwm output signals a) and b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 13. t imer 1 s input capture mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 14. por tgd logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 15. multi-input w ak eup (miw) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 16. core program model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 17. basic interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 18. programming mode pin con gurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 19. programming protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 20. serial data t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 21. p age mode protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 22. internal oscillator frequenc y (f osc ) vs. t emperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 23. icc acti v e vs. t emperature (no pll or data eepr om writes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 24. icc acti v e vs. t emperature (no pll, with data eepr om writes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 25. icc acti v e vs. t emperature (with pll, no data eepr om writes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 26. halt current vs. t emperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 figure 27. idle current vs. t emperature (no pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 28. idle current vs. t emperature (with pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 29. v ol vs. i ol @ 25? (g1?4, g6, g7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 30. v ol vs. i ol @ 25? (g0, g5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 figure 31. v oh vs. i oh @ 25? (g1?4, g6, g7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 32. v oh vs. i oh @ 25? (g0, g5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 figure 33. bor le v el vs. t emperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 34. programmable comparator v oltage le v el vs. t emperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 35. v ref vs. t emperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 36. current source (i src ) vs. t emperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 37. gain 16 error vs. t emperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 product specification fms7401l rev. 1.0.3 1/24/05 7 list of tables table 1. def ault re gister states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. cmode bit de nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. pll frequency selection (f pll /f osc = 2mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. hal t re gister de nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5. adcntrl1 re gister bit de nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6. analog input channel selection (a chsel[3:0]) bit de nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7. adcntrl2 re gister bit de nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8. programmable comparator (comp) control re gister bit de nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 9. programmable comparator lower voltage reference v thl (levels 1 ?31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 10. programmable comparator upper voltage reference v thu (levels 32 ?63) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 11. digital delay (ddela y) re gister bit de nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 12. prescale (pscale) re gister bit de nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 13. pll divide factor selection bits and the f t1clk resolution (f osc =2 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 14. t imer 1 prescale selection (ps) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 15. dead t ime (dtime) re gister bit de nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 16. t imer 1 control (t1cntrl) re gister bit de nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 17. t imer 1 mode con guration bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 18. t imer 0 control (t0cntrl) re gister de nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 19. w atchdog service re gister (wdsvr) de nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 20. i/o re gister bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 21. i/o con guration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 22. multi-input w ak eup (miw) re gister bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 23. interrupt priority sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 24. instruction addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 25. instruction cycles and bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 26. initialization re gister 1 bit de nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 27. initialization re gister 3 bit de nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 28. initialization re gister 4 bit de nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 29. t1hs1 (g0) and t1hs2 (g5) def ault con guration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 30. memory mapped re gisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 31. memory mapped re gisters and their re gister bit de nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 32. programming interf ace electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 33. 32-bit command and response w ord . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 fms7401l product specification 8 rev. 1.0.3 1/24/05 1 reset circuit the reset circuit in the fms7401l contains four input conditions that trigger a main system reset. when the main system reset is triggered, a sequence of events occur defaulting all memory mapped registers (including the initialization registers) and i/ os to their initial states (see t able 1 ). during the system reset sequence, the instruction core execution is halted allowing time for the internal oscillator and other analog circuits to stabilize. once the system reset sequence completes, the device will begin with its normal operation executing the instruction program residing in the code eeprom memory. the time required for the system reset sequence to complete (t reset ) is dependent on the individual trigger condition and is de?ed in the electrical characteristics section of the datasheet. the four reset trigger conditions are as follows: ? o wer-on reset (por) external reset 1 brown-out reset (bor) ? atchdog reset 2 ta b le 1. default register states 1.1 power-on reset circuit the power-on reset (por) circuit maintains the device in a reset state until vcc reaches a voltage level high enough to guaran- tee proper device operation. the por circuit is sensitive to the different vcc ramp rates and must be within s vcc as speci?d in the electrical characteristics section of the datasheet. the por circuit does not generate a system reset when vcc is falling. this feature is performed by the brown-out reset (bor) circuit and must be enabled by the boren bit of the initialization register 1. 4 in the case where vcc does not drop to 0v before the next power-up sequence, it is necessary to enable the bor circuit and/or reset the device externally through the reset pin. 1 1.2 external reset 1 the device may be externally reset through the reset input pin if the por/bor circuits cannot be used to properly reset the device in the application. the reset input pin contains an internal pull-up resistor making it an active low signal. therefore, to issue a device system reset the reset input should be held low for at least 10? before being released (i.e. returned to a high state). while the reset input is held low, the internal oscillator and other analog circuits are kept in a low power state reducing the current consumption of the device (a state resembling halt mode). in addition, the i/o pins are all initialized to an input tri-state con?uration unless defaulted otherwise. 5 at the rising edge of the reset input signal, the main system reset sequence is triggered releasing the internal oscillator and other analog circuits so that they may be initialized and begin the ir normal operation. 1.3 brown-out reset circuit the brown-out reset (bor) circuit is one of the on-chip analog comparator peripherals and must be enabled through the boren bit of the initialization registers 1. 4 the bor circuit is used to hold the device in a reset state when vcc drops below a ?ed threshold de?ed in the electrical characteristics section of the datasheet. while in reset, the device is held in its initial condition until vcc rises above the ?ed/power-on threshold. shortly after vcc rises above the ?ed/power-on threshold, the internal system reset sequence is started. once the system reset sequence completes, the device will begin with its normal operation executing the instruction program residing in the code eeprom memory. p eripheral/register external reset por g1, g2, g3, g4, g6, g7 high-impedance input (tri-state input) g0, g5 de?ed by init reg. 4 (see t ab le 28 ) sram memory no change unspeci?d stack pointer 0xf 0xf status register 0x80 0x80 t1cmpa, t1cmpb and t1ra registers 0xfff 0xfff dtime register 0x1f 0x1f all other memory mapped register not listed above. 3 0x00 0x00 product specification fms7401l rev. 1.0.3 1/24/05 9 the bor circuit should be used in situations when vcc rises and falls slowly and in situations when vcc does not fall to 0v before rising back to the device s normal operating range. the bor circuit can be thought of as a supplement function to the por circuit if vcc does not fall below 0.7v. figure 2. bor and por circuit relationship diagram 1. available only on the 14-pin package option. 2. refer to the timer 0 circuit section of the datasheet for details regarding the watchdog reset. 3. refer to table 30 of the device memory section of the datasheet for the detailed memory map. 4. refer to the device memory section of the datasheet for details regarding the initialization register 1. 5. refer to table 28 and table 29 of the device memory section of the datasheet for details. v cc (pin 8) bor r eset c i r c u i t o u t p u t global r eset t o l o g ic ex te r n al r eset pin ( 14- pin o n l y ) b a o u t p u t p or (pin 7 ) o u t p u t v cc t i m e bor o u t p u t 1 . 7 5 0 v cc v cc 0 p or o u t p u t p or o u t p u t p u l se 3 . 0 v 0 v cc 3 . 0 v 0 t h e r eset ci r c u i t w i ll t r i gg e r wh e n in p u ts a o r b t r a n s i t i o n f r o m h i g h t o l o w . a t t h a t t i m e t h e global r eset s i g n al w i ll g o h i g h wh ic h w i ll r eset all c o n t r oll e r lo g ic . t h e global r eset w i ll g o h i g h a n d st a y h i g h f o r a r o u n d 1 s . v cc fms7401l product specification 10 rev. 1.0.3 1/24/05 2 clock circuit the fms7401l may be clocked using its internal oscillator circuit or using an external digital clock signal. the desired clock source is selectable by the cmode bit of the initialization register 1. 1 during the reset sequence, the cmode bit is updated and the desired clock source (also called the device reference clock or f rclk1 ) takes control of the device. all devices are defaulted from the factory to use the internal oscillator as their main system instruction clock source. after power-up, the in ter- nal oscillator runs continuously unless entering halt mode or using an external clock source. ta b le 2. cmode bit de?ition the internal oscillator signal is factory trimmed to yield the f osc frequency as speci?d in the electrical characteristics section of the datasheet. if the external digital clock is selected, the input signal must have a 50/50 duty cycle, can range from dc t o the f osc , and must be available upon power-up. when the device is driven using an external clock source, the clock input to the device should be provided through the ain3/g1 input. once the source of f rclk1 is selected, the clock is then used as the reference clock for the pll, the clock to the digital ?ter in the programmable comparator circuit, and is divided-by-2 to be used as the main system instruction clock (f iclk ) of the device (see figure 3 and figure 4 ). 2.1 pll the fms7401l has an internal digital clock multiplier (pll) that steps-up the f rclk1 frequency by a multiplication factor of 32. the multiplied pll output is then divided by a factor of 1, 2, 4, and 8 in order to generate its programmable output fre- quencies that may be used as the main system instruction clock or by the pwm timer 1 circuit. the pll provides the ability to run the pwm timer 1 circuit at a frequency as high as 64mhz while the rest of the device operates at a much slower frequency k eeping the total current consumption low. the reference clock of the pll is de?ed by the f rclk2 signal (as shown in figure 3 and figure 4 ) and sourced by the f rclk1 signal. in order to yield the proper output frequencies offered by the pll, f rclk2 must operate at the f pll frequency as speci- ?d in the electrical characteristics section of the datasheet. in the case that f rclk1 is operating at the upper f osc frequency, 2 the refby2 bit in the adcntrl2 register 3 must be set in order to divide the f rclk1 by 2 to yield the appropriate f pll fre- quency of the f rclk2 signal. once the refby2 bit is set, the f rclk2 signal that drives the pll and digital ?ter in the pro- grammable comparator circuit operates at a f rclk1 /2 frequency. if an external digital clock is sourcing f rclk1 , the input signal must be supplied at the speci?d f osc frequency in order to meet the speci?d f pll frequency of the f rclk2 signal. ta b le 3. pll frequency selection (f pll /f osc = 2mhz) the pll outputs may be used to clock both the pwm timer 1 circuit and the main system clock. however, the pll must ?st be enabled by setting the pllen bit of the pscale register. 4 once set, the pll is turned on and begins the locking phase. before using any of the pll outputs, software must wait the t pll_lock to ensure that the pll is locked into its appropriate fre- quency and in phase. the pllen bit may not be changed while the pwm timer 1 circuit is in run mode. 5 any write attempts to this bit during this condition will not change its value. the pwm timer 1 circuit may be clocked either by the pll s f pwmclk output or by the main system clock (f iclk ). the fsel bit of the pscale register 4 selects between the pll s f pwmclk output (if fsel=1) or f iclk (if fsel=0). the fsel bit may not be set if the pll is not enabled (pllen=0) or changed while the pwm timer 1 circuit is in run mode. 5 any write attempts to this bit during these conditions will not change its value. cmode f rclk1 clock source 0 internal oscillator (@ f osc ) 1 external digital clock (g1/ain3) fs[1:0] f rclk2 f iclk (fmode = 0) f iclk (fmode = 1) f pwmclk 00 2 mhz 1 mhz 8 mhz 8 mhz 01 2 mhz 1 mhz 8 mhz 16 mhz 10 2 mhz 1 mhz 8 mhz 32 mhz 11 2 mhz 1 mhz 8 mhz 64 mhz product specification fms7401l rev. 1.0.3 1/24/05 11 the fs[1:0] bits of the pscale register 4 select the divide factor for the f pwmclk output (see t able 3 ). the fs bits may be changed by software at any time; however, if the pwm timer 1 circuit is in run mode the fs[1:0] value will not change the f pwmclk output frequency until after the pwm cycle ends (once the tmr1 counter over?ws). the last fs[1:0] value at the pwm cycle end time will dictate the divide factor of the f pwmclk output for the next pwm cycle. when reading the fs[1:0], the value reported will be the last value written by software (it may not necessarily re?ct the divide factor for the current pwm cycle). the main system instruction clock (f iclk ) source may be provided by the internal oscillator (f osc ) or the pll s f (fs=0) output with the same divide factor as the fs[1:0] = 00 selection. 6 the fmode bit of the pscale register 4 selects between the f (fs=0) (if fmode=1) or f rclk1 divided-by-2 signal. with the fmode bit enabled, it is possible to execute instructions at a speed eight times faster than the standard. the fmode bit may not be set if the pll is not enabled. 5 any attempts to write to fmode while pllen=0 will force fmode=0 ignoring any set instruction. once the pll has been enabled, software may change f iclk ? source on-the-? during normal instruction execution in order to speed-up a particular action. in order to synchronously disable the pll clocking structure, software must clear fsel and fmode before clearing the pllen bit in order to disable the pll successfully e.g. using separate instructions like ?bit pllen, pscale.?there are also special conditions for halt/idle power saving modes that must also be considered. please refer to the po wer sa ving modes section of the datasheet for details. figure 3. internal clock scheme f pwmclk digital c lock m u lti p li er ( pll ) f s[1] f s[ 0 ] di v i d e by 2 pll en f s e l f m o d e r e f by 2 f i clk y s e l a b a b y s e l a b s e l y f r clk 1 f ( f s = 0 ) f r clk 2 c lock t r i mm i n g i n i t 2 i n t er n al o s cillato r f t 1 clk ( f pll ) ( f o s c ) fms7401l product specification 12 rev. 1.0.3 1/24/05 figure 4. external clock scheme 1. refer to the device memory section of the datasheet for details regarding the initialization registers 1. 2. the upper f osc frequency (4mhz) is not a standard feature offered on the fms7401l devices but is available upon request. 3. the adcntrl2 register is defined in the adc circuit section of the datasheet. 4. the pscale register is defined in the pwm timer 1 circuit section of the datasheet. 5. software must always configure the device? entire clocking structure (see figure 3 and figure 4 ) while the pwm timer 1 circuit is off (t1c0=0) and configured in pwm mode (t1c3=0). 6. the pll? f (fs=0) output is not affected by the fs[1:0] bit value of the pscale register and merely shares the fs[1:0]=00 divide factor. f pwmclk digital c lock m u lti p li er ( pll ) f s[1] f s[ 0 ] di v i d e by 2 pll en f s e l f m o d e r e f by 2 y a b s e l f r clk 2 a b s e l y a b y s e l f i clk f ( f s = 0 ) f r clk 1 f t 1 clk g 1 / a i n 3 ( f pll ) product specification fms7401l rev. 1.0.3 1/24/05 13 3p o wer saving modes the fms7401l has both halt and idle power saving modes. each mode is controlled by software and offers the advantage of reducing the total current consumption of the device in an application. for all current consumption details, please refer to th e electrical characteristics section of the datasheet. 3.1 halt mode halt mode is a power saving feature that almost completely shuts down the device for current conservation. the device is placed into halt mode by setting the halt enable bit (ehalt) of the halt register using either the ?d m, #?or the ?bit #, m?instructions in the software. ehalt is a write only bit and is automatically cleared upon exiting halt mode. when enter- ing halt mode, the internal oscillator and all other on-chip systems including the programmable comparator (comp) and brown-out reset (bor) circuits are shut down. the device can exit halt mode only by the multi-input wakeup (miw) circuit. 1 therefore, prior to entering halt mode, soft- w are must ?st con?ure the miw circuit. after a wakeup from halt mode, a t halt_rec 2 start-up delay is initiated to allow the internal oscillator and other analog circuits to stabilize before normal device execution resumes. immediately after exiting ha lt mode, software must clear the power mode clear (pmc) register by using only the ?d m, #?instruction (see figure 5 ). tab le 4. halt register definition figure 5. recommended halt/idle flow 3.1.1 pll steps for halt mode when using halt mode and the pll in an application, software must take the appropriate steps in order to keep the integrity of the clock structure before entering and after exiting halt since the pll must be disabled. while in halt mode, all other device circuits except for the miw are disabled. once the pll is disabled, all output frequencies are turned off. if the pll is re- halt register (addr. 0xb7) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved eidle ehalt normal mode halt mode resume normal mode ld halt, #01h ld pmc, #00h multi-input wak eup normal mode idle mode resume normal mode ld pmc, #00h timer 0 overflow multi-input wak eup ld halt, #02h fms7401l product specification 14 rev. 1.0.3 1/24/05 enabled, it must complete the lock phase before software may enable the use of the outputs to clock any of the device circuits. therefore, upon exiting halt mode software must wait the t pll_lock 2 to ensure that the pll is locked into its appropriate frequency and in phase. 1. initially, the pllen bit of the pscale register must be set in order to enable the pll circuit. 2. if the pll outputs are to be used to clock any of the device circuits, fmode and/or fsel of the pscale register must be set after the appropriate t pll_lock wait time. 3 3. prior to entering halt mode, software must clear both fmode and fsel (the pwm timer 1 must be disabled in order to clear either bit) keeping the pllen bit 1. 4. using a separate instruction (e.g. rbit pllen, pscale) disable the pll by clearing the pllen bit. 5. software may then instruct the device to enter halt mode. 6. if all disabled circuits must be re-enabled after exiting from halt mode, repeat all initial steps enabling all circuits in the appropriate order as well as waiting t pll_lock . 3.2 idle mode in addition to the halt mode power saving feature, the device also supports an idle mode operation. the device is placed into idle mode by setting the idle enable bit (eidle) of the halt register through software using either the ?d m, #?or the ?bit #, m?instructions. eidle is a write only bit and is automatically cleared upon exiting idle mode. the idle mode operation is similar to halt mode except the internal oscillator, pll, and timer 0 circuits remain active while the other on-ch ip systems including the programmable comparator (comp) and brown-out reset (bor) circuits are shut down. the device exits idle mode automatically by the timer 0 idle over?w every 8192 cycles and by the multi-input wakeup (miw) circuit. 1 software must ?st con?ure the miw prior to entering idle mode in order to wake the device from idle with- out waiting for the over?w to occur. once a wake from idle mode is triggered, the normal device execution resumes by the next clock cycle. immediately after exiting idle mode, software must clear the power mode clear (pmc) register by using only the ?d m, #?instruction (see figure 5 ). 3.2.1 pll steps for idle mode when using idle mode, the pll does not need to be disabled prior to entering idle as it does with halt mode. the pll may remain enabled the entire time the device is in idle; however, the device will consume additional current. if current consump- tion is important, consider using halt instead of idle mode or at least disabling the pll while in idle. by keeping the pll enabled while in idle mode, the pll s outputs remain ready for use at any moment. with the pll s out- puts available, software has the option to source the main system clock (f iclk ) by the pll s f (fs=0) output when the fmode bit of the pscale register is set. 3 in addition, if the pll s f pwmclk output is clocking the pwm timer 1 circuit, 4 the timer may remain operational while in idle mode. however, the total current consumption will increase, hence the recommendation to disable the pwm timer 1 before entering idle mode. in contrast, if f iclk is clocking the pwm timer 1, the timer circuit ex ecution (like the main system controller) is stopped during idle. whether the pwm timer 1 is operational or not during idle mode, the instruction execution is stopped therefore all pending ?gs, etc. cannot be serviced. if the pll is to be disabled prior to entering idle mode, software must take the appropriate steps in order to keep the integri ty of the clock structure. once the pll is disabled, all output frequencies are turned off. if the pll is re-enabled, it must com- plete the lock phase before software may enable the use of the outputs to clock any of the device circuits. therefore, upon exi t- ing idle mode software must wait the t pll_lock to ensure that the pll is locked into its appropriate frequency and in phase. product specification fms7401l rev. 1.0.3 1/24/05 15 1. initially, the pllen bit of the pscale register must be set in order to enable the pll circuit. 2. if the pll outputs are to be used to clock any of the device circuits, fmode and/or fsel of the pscale register must be set after the appropriate t pll_lock wait time. 3. prior to entering idle mode, software must clear both fmode and fsel (the timer must be disabled in order to clear either bit) keeping the pllen bit 1. 4. using a separate instruction (e.g. rbit pllen, pscale) disable the pll by clearing the pllen bit. 5. software may then instruct the device to enter idle mode. 6. if all disabled circuits must be re-enabled after exiting from idle mode, repeat all initial steps enabling all circuits in t he appropriate order as well as waiting t pll_lock . 1. the miw and timer 0 circuits are described later in the datasheet. 2. refer to the electrical characteristics section of the datasheet for details. 3. refer to the clock circuit? pll section of the datasheet for details. 4. the fsel bit in the pscale register must be set. fms7401l product specification 16 rev. 1.0.3 1/24/05 4 adc circuit the analog-to-digital converter (adc) circuit extends the features of the fms7401l by offering a 5-channel 8-bit adc. the adc may be programmed to convert voltages on any of the eight inputs of the analog mux, where ?e are multifunction input channels (ach1-ach5) and three are used for system calibration. the integrated adc function offers a single cost-effective solution for applications requiring voltage, current and temperature sensing. the multifunction input channels may be con?- ured to perform standard conversions on any of the analog input pins (g4/ain0, g3/ain1, g2/ain2, g3/ain3 or g7/ain4). three of the multifunction input channels may be programmed to perform adc conversions through the internal autozero ampli?r, uncommitted ampli?r, and current source generator for special control system and battery management applica- tions (see figure 6 ). the adc circuit s eight analog inputs are software selectable where their analog input voltage is converted with respect to the internal adc reference voltage (v aref ). v aref may be programmed to use the internal bandgap reference voltage (v ref ) or vcc as its source. by default, the adc circuit s v aref is con?ured to use the internal v ref as its source. 1 the adc performs conversions of 8-bit resolution with accuracy as de?ed in the electrical characteristics section of the datasheet. for a standard adc conversion, the adc circuit converts the analog input voltage in a total of 13 conversion clock c ycles, and a total of 20 conversion clock cycles when performing an autozero adc conversion. to yield a better adc conver- sion accuracy, the adc circuit may con?ure the adc clock (f adclk ) to a slower frequency, lengthening the total conversion time while improving its accuracy. as part of the total conversion time, the adc circuit completes a sample and hold phase to measure fast changing analog signals before converting the voltage. an adc conversion can be initiated by a software com- mand or automatically (using the gated auto-sampling mode) by the active (on) edge transition of the adstrobe pwm t imer 1 output. 2 if enabled, the adc circuit offers the use of its microcontroller hardware interrupt (adci) triggered after each completed adc conversion so that the microcontroller core is freed to perform other tasks. 4.1 adc circuit con?uration software must access the three memory mapped adc registers to con?ure and control the adc circuit. 3 the adc control 1 (adcntrl1) register is used to select the analog input channel and adc reference voltage (v aref ) for the conversion. in addition, it is used to initiate a conversion through software, monitor the adc pending ?g, and enable the adc circuit s microcontroller hardware interrupt (adci). the adc control 2 (adcntrl2) register is used to enable the internal autozero ampli?r, uncommitted ampli?r, current source generator, and/or adc auto-sampling mode. the adcntrl2 register is also used to divide the adc f adclk clock to improve the conversion accuracy. lastly, the adc data (adata) register is used by software to read the ?al converted 8-bit digital value. adata is a read only register and is updated automatically at the e nd of each adc conversion. product specification fms7401l rev. 1.0.3 1/24/05 17 figure 6. adc block diagram 4 4.1.1 adcntrl1 register the adcntrl1 is an 8-bit memory map register used to con?ure and control the adc circuits. software has both read and write access to all bits of the register. bit 7 of the adcntrl1 register is the adc pending (apnd) ?g and is triggered after the 8-bit converted digital value is latche d to the adata register towards the end of the adc conversion cycle. the apnd bit may be used by software to monitor when to access adata or to issue microcontroller hardware interrupts (if enabled). in order for software to monitor apnd, it must be cleared b efore the next converted value is latched in adata where the apnd ?g is set to 1. 4 8 vcc a b y sel b v oltage level generator +v ref complev 6 sel ach2 ach3 ach4 ach1 ach5 agnd y analog voltage generator sar logic +v aref core bus 8 programmable delay pwmoff deltime f rclk2 g3/ain1 g2/ain2 g1/ain3 ac hsel[3:0] +v ref vcc +v aref refsel g4/ain0 + - s/h adstrobe a y sel gnd +v ref r r x16 gain a utozero amplifier 2r r vcc enis a ch5 vcc/3 + _ g6/-a in +v ref 0.23r r vloop sr_gnd + _ compsel g7/ain4/a out +v ref enamp ach5 fms7401l product specification 18 rev. 1.0.3 1/24/05 bit 6 of the adcntrl1 register is the adc s microcontroller hardware interrupt enabled (ainten) bit. if set, hardware interrupts (adci) are enabled and triggered by the apnd pending ?g. 5 as long as the adc pending ?g is set, the hardware interrupt will continue to execute software s adc interrupt service routine until the pending ?g is cleared. 6 bit 5 of the adcntrl1 register is the adc conversion start/busy (astart) bit. software must set the astart bit to ini- tiate an adc conversion when the endas bit of the adcntrl2 register is set to 0. the astart bit will remain high as long as an adc conversion is in progress (whether software or the adstrobe signal triggered the conversion). if software attempts to clear the astart bit while a conversion is in progress, the write command is ignored and the astart bit remains high until the conversion cycle completes. software should monitor astart to determine when the conversion has completed instead of the apnd bit. the apnd bit may be triggered before the astart is automatically cleared. the adc conversion completion delay may occur when the f iclk clock is slower than an adc conversion clock cycle. bit 4 of the adcntrl1 register is the adc voltage reference selection (refsel) bit. if refsel=0, the adc reference v oltage (v aref ) becomes sourced by the internal bandgap voltage reference (v ref ). if refsel=1, the adc reference voltage (v aref ) becomes sourced by vcc. if the adc circuit is performing a conversion, software must avoid writing to the refsel bit. bits 3-0 of the adcntrl1 register are the analog channel selection (achsel[3:0]) bits selecting one of the eight analog input channels to convert its voltage (see t able 6 ). software may write to the achsel bits at any time; however, the actual a chsel selection signals will not change while an adc conversion is in progress. if a read command is issued while a con- v ersion is in progress, the current value of the achsel bits may not necessarily re?ct the actual state of the achsel selec- tion signals. the last value of the achsel bits written by software at the time of the adc conversion trigger, dictates the sta te of the achsel selection signals for the triggered adc conversion cycle. the sbit or rbit instructions may be used to either set or clear one of the adcntrl1 register bits, like the ainten bit. the sbit and rbit instructions both take two instruction clock cycles to complete their execution. in the ?st cycle, all regis - ter bits are automatically read to obtain their most current value. in the second cycle, the bit to be set/cleared is given its new v alue and all bits are then re-written to the register. using the sbit/rbit instruction to set/clear an enable bit with a pendi ng ?g in the same register may cause a potential hazard. software may inadvertently clear a recently triggered pending ?g if the trigger happened during the second phase of the sbit/rbit instruction execution. to avoid this condition, the ld instruction must be used to set or clear the interrupt enable bit. the adc circuit is designed such that software may not trigger a pending ?g by writing a 1 to the apnd bit, it may only be cleared. the action of writing a 1 to the apnd register bit holds its curren t bit value. the action of writing a 0 to the apnd register bit clears the bit value. therefore, the ?d t1cntrl, #0e0h? instruction will set the astart and ainten bits without clearing apnd. product specification fms7401l rev. 1.0.3 1/24/05 19 ta b le 5. adcntrl1 register bit de?itions ta b le 6. analog input channel selection (achsel[3:0]) bit de?itions 4.1.2 adcntrl2 register the adcntrl2 is an 8-bit memory map register used to con?ure the analog circuits. six of the eight register bits are used to con?ure circuits directly related to the adc circuit while the others are not related. bit 7 (refby2) of the adcntrl2 register is the reference clock (f rclk1 ) divide-by-2 enable bit. the refby2 bit con?- ures the reference clock of the pll and programmable comparator circuit to be sourced either by f rclk1 or f rclk1 /2 clock. refer to the clock circuit section of the datasheet for additional details. bit 6 (compsel) of the adcntrl2 register is the programmable comparator s non-inverting input selection bit. if compsel=0, the non-inverting input of the programmable comparator is the g4/ain0 device pin. if compsel=1, the non-inverting input of the programmable comparator is the g2/ain2 device pin. before enabling the programmable comparator circuit, the selected analog input port pin must be con?ured as a tri-state input bypassing the i/o circuitry. 9 refer to the programmable comparator circuit section of the datasheet for addition details. bit 5 of the adcntrl2 register is the uncommitted ampli?r enable (enamp) bit. if enamp=0, the uncommitted ampli- ?r circuit is disabled and its pin connections (g6/-a in and g7/a out ) may be used as normal i/o ports. the g7/ain4 pin may still be used as a standard adc conversion input through the analog ach5 channel. if enamp=1, the uncommitted ampli?r circuit is enabled and its pin connections must be con?ured as tri-state inputs where g6/-a in is the inverting input and g7/ a out is the ampli?r output. 9 if the adc circuit is performing a conversion on the analog ach5 input when driven by the uncommitted ampli?r, software must avoid clearing the enamp bit. refer to the following uncommitted ampli er section for additional details. bit 4 (endas) of the adcntrl2 register enables the adc conversion s gated auto-sampling operating mode. if endas=1, the adc circuit con?ures the f adclk clock for synchronization with the pwm timer 1 s adstrobe output signal. the adc circuit will then accept triggers by the active (on) edge transition of the adstrobe signal. all other adc con?uration adcntrl1 register (addr. 0x9f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 apnd ainten astart refsel achsel[3:0] bit description apnd (0) adc? pending flag is cleared. (1) adc? pending flag is triggered. ainten (0) disables adc hardware interrupts. (1) enables adc hardware interrupts. astart (0) adc conversion is not in progress. (1) start an adc conversion / adc conversion in progress. refsel (0) adc reference (v aref ) = internal v ref (1) adc reference (v aref ) = vcc achsel[3:0] analog input channel selection bits. refer to table 6 for details. a chsel[3] achsel[2] achsel[1] achsel[0] analog channel i/o equiv. 00 00 a ch1 g4/ain0 00 01 a ch2 g3/ain1 00 10 a ch3 g2/ain2 00 11 a ch4 g1/ain3 10 00 a ch5 g7/ain4/a out 10 01 gnd - 10 10+v ref - 11 00 vcc/3 - fms7401l product specification 20 rev. 1.0.3 1/24/05 options must be prepared prior to setting the endas bit. refer to the following adc gated auto-sampling mode section for additional details. the adstrobe signal is generated by the pwm timer 1 circuit and is con?ured using its t1cmpb and t1ra registers. refer to the pwm t imer 1 circuit section of the datasheet for details regarding its operation. if endas=0, the adc circuit is con?ured to accept only adc start commands issued by software when setting the astart bit of the adcntrl1 register to 1. refer to the following adc con v ersion modes section for additional details. bits 3 and 2 (aspeed[1:0]) of the adcntrl2 register selects the divide factor (1, 2, 4, or 8) to slow the f adclk clock e xtending the adc conversion cycle time. in most cases, the f adclk clock division is performed to improve the adc conversion accuracy. refer to the following adc con v ersion clock con guration section for addition details. bit 1 of the adcntrl2 register is the current source generator enable (enis) bit. if enis=0, the current source generator circuit is disabled and its g3/ain1 pin may be used as a normal i/o port or as a standard adc conversion input through the analog ach2 channel. if enis=1, the current source generator circuit is enabled and its pin connection must be con?ured as a tri-state input bypassing the i/o circuitry. 9 if the adc circuit is performing a conversion on the analog ach2 input when driven by the current source generator, software must avoid clearing the enis bit. refer to the following current source generator section for additional details. bit 0 (gain) of the adcntrl2 register is the autozero ampli?r enable bit. if gain=0, the autozero ampli?r with its gain 16 circuitry is disabled where its g4/ain0 pin connections may be used as a normal i/o port. the g4/ain0 pin may still be used as a standard adc conversion input through the analog ach1 channel. if gain =1, the autozero ampli?r with its gain 16 circuitry is enabled and its g4/ain0 pin connection must be con?ured as a tri-state input where g4/ain0 is the non- inverting and sr_gnd is the inverting input of the ampli?r. 9 software may write to the gain bit at any time; however, the actual gain enable signal will not change while an adc conversion is in progress. if a read command is issued while a con- v ersion is in progress, the current value of the gain bit may not necessarily re?ct the actual state of the gain enable signal . the last value of the gain bit written by software at the time of the adc conversion trigger, dictates the state of the gain enable signal for the triggered adc conversion cycle. refer to the following autozero ampli er section for additional details. product specification fms7401l rev. 1.0.3 1/24/05 21 ta b le 7. adcntrl2 register bit de?itions 4.2 adc conversion modes the adc circuit may be con?ured to convert analog voltages with a conversion cycle time determined by the adc clock (f adclk ) and the aspeed bits of the adcntrl2 register. refer to the following adc con v ersion clock con guration section for details. by default, the adc circuit performs a conversion with every trigger initiated by software setting the astart bit of the adcntrl1 register to 1. the adc circuit may also be con?ured to perform a conversion automatically (using the gated auto-sampling mode) with every active (on) edge of the pwm timer 1 adstrobe output signal. refer to the following adc gated auto-sampling mode section for details. before any adc conversion triggers are issued (by software or automatically) software must con?ure the voltage reference (v aref ) and analog input channel appropriately. this is done by programming the refsel and achsel bits of the adcntrl1 register. if using the internal autozero ampli?r, uncommitted ampli?r, and current source generator circuits in the application, software must also con?ure and enable the desired circuits. lastly, the f adclk must be con?ured to improve the adc conversion accuracy. when performing an adc conversion where software triggers the conversion, the astart bit of the adcntrl1 register remains high (1) symbolizing that a conversion is in progress. the adc conversion is divided in two phases lasting a total of 13 conversion clock cycles. however, an autozero adc conversion lasts a total of 20 conversion clock cycles. refer to the fol- lowing autozero ampli er section for details. in the ?st phase of a standard conversion, occupying the ?st four conversion c ycles, the adc circuit performs a sample and hold operation to measure fast changing analog signals before converting the input voltage. the second phase, occupying the last nine cycles, converts the analog input voltage to an 8-bit digital value an d stores it in the adata register for easy access by software. once the converted value is stored in adata, the apnd bit is trig- gered and astart bit is cleared (symbolizing completion of the conversion cycle). software cannot rely on the apnd bit for adcntrl2 register (addr. 0xa0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 refby2 compsel enamp endas aspeed[1:0] enis gain bit description refby2 used to divide the reference clock for the pll and digital filter of the programmable comparator circuit. refer to the clock circuit section of the datasheet for details. (0) f rclk2 =f rclk1 (1) f rclk2 =f rclk1 /2 compsel (0) g4 is connected to the programmable comparator? non-inverting input. (1) g2 is connected to the programmable comparator? non-inverting input. enamp (0) disables the uncommitted amplifier (g6 and g7 are normal i/os). (1) enables the uncommitted amplifier where g6/-a in is the inverting input and g7/a out is the amplifier output. the amplifier output (a out ) is also the ach5 input to the adc? analog mux. endas (0) enables the standard adc conversion mode where software must trigger an adc conversion by setting the astart bit of the adcntrl1 register. (1) enables the adc gated auto-sampling mode where pwm timer 1? adstrobe output to automatically triggers an adc conversion. aspeed[1:0] (0) adc conversion clock speed = f adclk (1) adc conversion clock speed = f adclk /2 (2) adc conversion clock speed = f adclk /4 (3) adc conversion clock speed = f adclk /8 enis (0) disable current source generator (g3 is a normal i/o). (1) enable current source generator where g3/ain1 sources the i src . gain (0) disables the autozero amplifier (g4 is a normal i/o). (1) enables the autozero amplifier (with a gain of 16) where g4/ain0 is its non-inverting input and sr_gnd is it inverting input. fms7401l product specification 22 rev. 1.0.3 1/24/05 this information because the apnd bit may be triggered before the astart is automatically cleared. the adc conversion completion delay may occur when the f iclk clock is slower than an adc conversion clock cycle. 4.2.1 analog input voltage and its 8-bit digital result the relationship between the 8-bit digital value stored in the adata register and the analog input voltage is as follows: ? adc is the 8-bit digital result of an adc conversion. ? a ch(x) is the analog voltage applied to the selected input channel. 4.2.2 adc gated auto-sampling mode the adc circuit may be con?ured in gated auto-sampling mode by setting the endas bit of the adcntrl2 register. when in auto-sampling mode, all adc conversions are automatically triggered by the active (on) edge transition of the pwm t imer 1 s adstrobe output signal. 2 if the period of the pwm adstrobe signal is less than the total adc conversion time, any triggers issued while a conversion is in progress (astart=1) are ignored. once the trigger is detected, the astart bit of the adcntrl1 register is set symbolizing that a conversion is in progress. the initial conversion phase, the sample and hold or autozero (if gain=1), begins after a 1? cycle delay. 7 once all eight digital bits are determined and stored in the adata register, the apnd ?g is set to trigger a hardware interrupt (if enabled) ?gging software that the adata register has been updated with the adc conversion results. once all phases of the adc conversion cycle completes, the astart bit is then automatically cleared by the adc circuit. since software cannot change the adc circuit con?uration while an adc con- v ersion is in progress, the astart bit must be monitored to determine when the conversion cycle completes. software cannot rely on the apnd bit for this information because the apnd bit may be triggered before the astart is automatically cleared. the adc conversion completion delay may occur when the f iclk clock is slower than an adc conversion clock cycle. 4.2.3 adc conversion clock configuration the adc conversion clock (f adclk ) is sourced either by the device s main system instruction clock (f iclk ) or the pwm timer 1 s clock (f t1clk ) depending on the adc circuit s operating mode. if the standard adc conversion mode is selected, the adc circuit is automatically con?ured to source the f adclk clock by the f iclk clock. if the adc conversion auto-sampling mode is selected, the adc circuit is automatically con?ured to source the f adclk clock by the f t1clk clock to synchronize the adc conversions with the active (on) edge of the pwm timer 1 adstrobe output signal. 2 when in standard adc conversion mode, the aspeed[1:0] bits of the adcntrl2 register may be used to slow the total con- v ersion time improving the adc conversion accuracy. however, if the f iclk clock is sourced by the pll s f (fs=0) output (when fmode=1) the f adclk will clock eight times faster than the proper conversion rate (1? cycle time). the f adclk clock must then be divided by setting the aspeed[1:0]=3 divide factor to yield a f adclk /8 conversion clock cycle. otherwise, software may temporarily clear fmode returning the conversion cycle to its proper frequency and free the aspeed bits to be used to improve the conversion accuracy. in addition, if the internal oscillator is trimmed to its upper f osc frequency and it is sourcing the f iclk clock, the aspeed[1:0]=1 divided factor must be selected to yield a f adclk /2 conversion clock cycle. 8 a greater divide factor may still be selected by setting the aspeed[1:0]>1. when in adc conversion auto-sampling mode, the adc circuit automatically con?ures the f adclk clock to be sourced by the f t1clk clock so that the adc conversions may be synchronized with the active (on) edge of the adstrobe signal. how- ev er, the f t1clk clock is ?st sent into a special divide circuit which evaluates its con?uration to determine the divide factor needed to yield the proper f adclk conversion rate (1? cycle time). the fmode, fsel, and fs bits of the pscale register are evaluated so that the divide circuit applies the appropriate divide factor to the f t1clk clock (the ps bits do not apply). the aspeed[1:0] bits of the adcntrl2 register may be used to slow the total conversion time improving the adc conversion v adc v ach x () v aref -------------------- - 255 = product specification fms7401l rev. 1.0.3 1/24/05 23 accuracy. however, if the internal oscillator is trimmed to its upper f osc frequency while fmode and fsel are zero, the aspeed[1:0]=1 divided factor must be selected to yield a f adclk /2 conversion clock cycle. 8 a greater divide factor may still be selected by setting the aspeed[1:0]>1. 4.3 autozero ampli?r the gain bit of the adcntrl2 register enables the autozero ampli?r circuit. to perform a proper adc conversion using the autozero ampli?r, software must con?ure its non-inverting input (g4/ain0) as a tri-state input bypassing the i/o circuitry. the autozero ampli?r has a gain of 16, but is not de?ed as a true differential ampli?r because the inverting sr_gnd input must be connected as close to ground as possible (e.g. to act as a kelvin connection) to reduce noise and improve the precision of the measurement. to perform an adc conversion through the autozero ampli?r, the ach1 input channel of the analog mux must be selected. the autozero adc conversion is divided in three phases lasting a total of 20 conversion clock cycles. in the ?st phase, occu- p ying the ?st six conversion cycles, it calculates the offset voltage of the ampli?r. the second phase, occupying the next ? e c ycles, adds or subtracts the offset voltage to the ampli?d input voltage which now has a gain of 16. the ?al phase, occupy- ing the last nine cycles, converts the autozero input voltage to an 8-bit digital value and stores it in the adata register for easy access by software. 4.4 uncommitted ampli?r the uncommitted ampli?r enable (enamp) bit of the adcntrl2 register enables the uncommitted ampli?r (amp) circuit whose inverting input is connected to the g6/-a in and output to the g7/a out port pins. before enabling the amp circuit, software must con?ure both the g6/-a in and g7/a out pins as tri-state input ports bypassing all i/o circuitry. the amp circuit may be used in any control or battery management applications. in control applications, the amp circuit is used as the error ampli?r in a hardware closed loop whose input connections are part of the external compensation loop circuit. the output of the ampli?r (a out ) is internally fed to the programmable comparator circuit to control the pwm t1hs1 and t1hs2 inputs of the control plant block. an adc conversion may be triggered to monitor a out by selecting the ach5 input channel of the analog mux. the amp circuit may be con?ured as a general uncommitted ampli?r whose non-inverting input is connected to v ref . therefore, the amp circuit may only amplify differences with respect to v ref . an adc conversion may be triggered to con- v ert the voltage at a out by selecting the ach5 input channel of the analog mux. in battery management applications, the amp circuit may be used to improve the resolution of the battery voltage measurement by adding a gain through the feedback loop. v oltage variation at a typical point will be ampli?d with a gain for better resolution, for example, to sense the negative del ta v (ndv) to determine the end of change for a nicd or nimh battery. 4.5 current source generator the current source enable (enis) bit of the adcntrl2 register enables the current source generator (isource) circuit connected to the g3/ain1 pin. before enabling the isource circuit, software must con?ure the g3/ain1 port as a tri-state input bypassing all i/o circuitry. 9 once the enis bit is set, the isource circuit begins to generate i src of current typically used to interface to an opto-coupler output. 1 figure 7 provides an example of a typical isource application where the v oltage developed at the g3/ain1 input can be converted by the adc circuit if the ach2 analog input channel is selected. the isource and adc circuit combination may also be used to measure capacitive sensors or the resistance of a thermistor (ntc/ptc) to indirectly measure the temperature. fms7401l product specification 24 rev. 1.0.3 1/24/05 figure 7. current generator interface 1. refer to the electrical characteristics section of the datasheet for details. 2. refer to the pwm timer 1 circuit section of the datasheet for details regarding the adstrobe signal configuration. 3. refer to table 30 of the device memory section of the datasheet for the detailed memory map. 4. on the fms7401l 8-pin device, the sr_gnd is internally bonded to the gnd pin. 5. hardware interrupts are not executed by the microcontroller core unless the global interrupt enable (g) flag of the status re gister is set. refer to the 8-bit microcontroller core section of the datasheet for details. 6. the adc hardware interrupt will be executed in the defined priority order. refer to the 8-bit microcontroller core section of the datasheet for details. 7. assuming the internal oscillator frequency is f osc =2mhz as specified in the electrical characteristics section of the datasheet. 8. the upper f osc frequency (4mhz) is not a standard feature offered on the fms7401l devices but is available upon request. 9. refer to the i/o ports section of the datasheet for details. g3/ain1 vcc control vo ltage analog mux adc product specification fms7401l rev. 1.0.3 1/24/05 25 5p r ogrammable comparator circuit the programmable comparator circuit is an analog comparator whose outputs may be monitored by software or fed into a dig- ital delay ?ter used to disable the pwm timer 1 circuit or its pwm cycle. the comparator s non-inverting input is software selectable by the compsel bit of the adcntrl2 register. 1 if compsel=0, the non-inverting input of the programmable comparator is the g4/ain0 device pin. if compsel=1, the non-inverting input of the programmable comparator is the g2/ ain2 device pin. before enabling the programmable comparator circuit, the selected analog input port pin must be con?ured as a tri-state input bypassing the i/o circuitry. 2 the inverting input of the comparator is controlled by the voltage loop (vloop) enable bit of the comparator control (comp) register. if vloop=0, the voltage loop is disabled and the inverting input of the analog comparator is con?ured as one of the 63 programmable voltage levels (v thl , v thu ). if vloop=1, the analog comparator is set in a voltage loop con?uration with the uncommitted (error) ampli?r output (a out ) connected to the comparator s inverting input (see figure 9 ). the programmable comparator circuit may be con?ured and controlled by software through the two 8-bit comparator control (comp) and digital delay (ddelay) registers. both the programmable comparator and the digital delay ?ter must be enabled by software by setting the comparator enable (compen) and clearing the epwm bits of the digital delay (ddelay) register. upon a system reset, the programmable comparator is disabled and the digital delay ?ter is enabled. the comp circuit is automatically disabled during halt mode. after exiting the halt mode, software must wait at least 10 instruction clock cycles before reading the cout bit to ensure that the internal circuit has stabilized. ta b le 8. programmable comparator (comp) control register bit de?itions 5.1 programmable comparator s voltage threshold levels (vloop=0) the programmable comparator circuit is con?ured to compare the g4/ain0 or g2/ain2 non-inverting input against the pro- grammable voltage threshold levels on its inverting input (see t able 9 and t able 10 ). the comparator output (c out ) is 1 when the g4/ain0 or g2/ain2 input pin rises above the selected voltage threshold. as long as the input stays above the selected v oltage threshold, the c out signal will hold its state. the c out signal will equal zero if the g4/ain0 or g2/ain2 input voltage f alls below the programmed threshold voltage or if the programmable comparator circuit is disabled. software may change the programmed threshold voltage on-the-? as needed in the application. if the digital delay ?ter circuit is enabled (epwm=0), the c out signal is monitored for its rising edge to generate the pwmoff signal. refer to figure 8 and the following digital delay filter with pwmoff output section for addition details. bit 6 of the adcntrl2 register is the programmable comparator non-inverting input selection (compsel) bit. 1 if compsel=0, the non-inverting input of the programmable comparator is the g4/ain0 device pin. if compsel=1, the non- inverting input of the programmable comparator is the g2/ain2 device pin. before enabling the programmable comparator circuit, the selected analog input port pin must be con?ured as a tri-state input bypassing the i/o circuitry. 2 comp register (addr. 0xa0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cl[5:0] vloop cout bit description cl[5:0] programmable comparator voltage reference level bits. refer to table 9 and table 10 for details. vloop (0) configures the inverting input of the analog comparator as one of the 63 programmable voltage levels (v thl , v thu ). (1) configures the analog comparator in a voltage loop configuration with the uncommitted amplifier output (a out ) connected to the inverting input. cout (0) g2/ain2 or g4/ain0 non-inverting input is less than inverting input configured by vloop. (1) g2/ain2 or g4/ain0 non-inverting input is greater than inverting input configured by vloop. fms7401l product specification 26 rev. 1.0.3 1/24/05 bits 7-2 (cl[5:0]) is the comparator voltage threshold level selection bits of the comparator control (comp) register. the cl bits may be programmed to select one of the voltage threshold levels as the inverting input of the analog comparator. refer to t able 9 and t able 10 for a detailed list of voltages. bit 1 of the comparator control (comp) register is the programmable comparator circuit s voltage loop (vloop) con?ura- tion enable bit. if vloop=0, the programmable comparator circuit is con?ured to compare the analog g4/ain0 or g2/ain2 input (compsel=0 or 1) to one of the 63 voltage threshold levels. if vloop=1, enables the voltage loop con?uration where the analog g4/ain0 or g2/ain2 input (compsel=0 or 1) to the uncommitted (error) ampli?r output (a out ). bit 7 of the digital delay (ddelay) register is the programmable comparator circuit enable (compen) bit. if compen=0, the programmable comparator circuit is disabled and the c out signal is low. if compen=1, the programmable comparator circuit is enabled and the c out signal generated by the comparison of the two inputs. the comparator output (c out ) signal is latched by the main system instruction (f iclk ) clock into bit 0 (cout) of the compar- ator control (comp) register. software may only read the cout bit to monitor the comparator s activity. the cout bit cannot cause a microcontroller hardware interrupt or perform any other action. figure 8. programmable comparator block diagram (vloop = 0) ddelay register 7 c l [5] 1 v l oop 0 c o ut a d ju st re f ere nc e v ol t a ge c o mp a r a t o r c on tr ol ( c o m p ) register g4/ a in 0 _ + d igi t al delay c i r c u i t 3 2 1 0 p w m o ff ( wk e n [ 6 ] ) dd [ 3 ] dd [ 2 ] dd [ 1 ] dd [ 0 ] f r c l k 2 5 e p w m e n 6 c l [ 4 ] 5 c l [ 3 ] 4 c l [ 2 ] 3 c l [ 1 ] 2 c l [ 0 ] a c h 5 g 2 / a in 2 c o m p s el ad c n t r l 2 [ 6 ] c o mp a r a t o r c o ut product specification fms7401l rev. 1.0.3 1/24/05 27 ta b le 9. programmable comparator lower voltage reference v thl (levels 1 ?31) level cl[5] cl[4] cl[3] cl[2] cl[1] cl[0] voltage reference 10 000 01 35mv 20 000 10 50mv 30 000 11 64mv 40 001 00 78mv 50 001 01 93mv 60 001 10 107mv 70 001 11 121mv 80 010 00 135mv 90 010 01 150mv 10 0 0 1 0 1 0 164mv 11 0 0 1 0 1 1 178mv 12 0 0 1 1 0 0 192mv 13 0 0 1 1 0 1 205mv 14 0 0 1 1 1 0 219mv 15 0 0 1 1 1 1 233mv 16 0 1 0 0 0 0 247mv 17 0 1 0 0 0 1 261mv 18 0 1 0 0 1 0 274mv 19 0 1 0 0 1 1 288mv 20 0 1 0 1 0 0 302mv 21 0 1 0 1 0 1 316mv 22 0 1 0 1 1 0 330mv 23 0 1 0 1 1 1 343mv 24 0 1 1 0 0 0 358mv 25 0 1 1 0 0 1 371mv 26 0 1 1 0 1 0 385mv 27 0 1 1 0 1 1 401mv 28 0 1 1 1 0 0 413mv 29 0 1 1 1 0 1 429mv 30 0 1 1 1 1 0 443mv 31 0 1 1 1 1 1 459mv fms7401l product specification 28 rev. 1.0.3 1/24/05 ta b le 10. programmable comparator upper voltage reference v thu (levels 32 ?63) 5.2 hardware voltage and current loop control (vloop=1) the programmable comparator circuit is con?ured to compare the g4/ain0 or g2/ain2 non-inverting input against the out- put of the uncommitted (error) ampli?r (a out ) when con?ured in a voltage/current loop control mode. in the voltage/cur- rent loop control, the inner (current) loop is performed by comparing the level on the g4/ain0 or g2/ain2 input against the v oltage present at the uncommitted (error) ampli?r (a out ). the uncommitted ampli?r performs the outer (voltage) loop control by detecting the error signal and driving the current control loop to modify the pwm duty cycle (see figure 9 ). the fms7401l voltage/current loop con?uration can be used in smps applications where the digital loop control does not have the required accuracy and speed. refer to the adc circuit section of the datasheet for the uncommitted ampli?r con?ura- tion details. when vloop=1, the comparator output (c out ) is 1 when the g4/ain0 or g2/ain2 input pin rises above a out . as long as the input stays above a out , the c out signal will hold its state. the c out signal will equal zero if the g4/ain0 or g2/ain2 input v oltage falls below a out or if the programmable comparator circuit is disabled. if the digital delay ?ter circuit is enabled (epwm=0), the c out signal is monitored for its rising edge to generate the pwmoff signal. refer to figure 9 and the following digital delay filter with pwmoff output section for addition details. level cl[5] cl[4] cl[3] cl[2] cl[1] cl[0] voltage reference 32 1 0 0 0 0 0 0.46v 33 1 0 0 0 0 1 0.51v 34 1 0 0 0 1 0 0.56v 35 1 0 0 0 1 1 0.61v 36 1 0 0 1 0 0 0.66v 37 1 0 0 1 0 1 0.71v 38 1 0 0 1 1 0 0.76v 39 1 0 0 1 1 1 0.81v 40 1 0 1 0 0 0 0.86v 41 1 0 1 0 0 1 0.91v 42 1 0 1 0 1 0 0.96v 43 1 0 1 0 1 1 1.01v 44 1 0 1 1 0 0 1.06v 45 1 0 1 1 0 1 1.11v 46 1 0 1 1 1 0 1.16v 47 1 0 1 1 1 1 1.21v 48 1 1 0 0 0 0 1.27v 49 1 1 0 0 0 1 1.32v 50 1 1 0 0 1 0 1.37v 51 1 1 0 0 1 1 1.43v 52 1 1 0 1 0 0 1.48v 53 1 1 0 1 0 1 1.53v 54 1 1 0 1 1 0 1.58v 55 1 1 0 1 1 1 1.63v 56 1 1 1 0 0 0 1.68v 57 1 1 1 0 0 1 1.73v 58 1 1 1 0 1 0 1.78v 59 1 1 1 0 1 1 1.83v 60 1 1 1 1 0 0 1.88v 61 1 1 1 1 0 1 1.94v 62 1 1 1 1 1 0 1.99v 63 1 1 1 1 1 1 2.04v product specification fms7401l rev. 1.0.3 1/24/05 29 bit 6 of the adcntrl2 register is the programmable comparator non-inverting input selection (compsel) bit. 1 if compsel=0, the non-inverting input of the programmable comparator is the g4/ain0 device pin. if compsel=1, the non- inverting input of the programmable comparator is the g2/ain2 device pin. before enabling the programmable comparator circuit, the selected analog input port pin must be con?ured as a tri-state input bypassing the i/o circuitry. 2 bit 1 of the comparator control (comp) register is the programmable comparator circuit s voltage loop (vloop) con?ura- tion enable bit. if vloop=0, the programmable comparator circuit is con?ured to compare the analog g4/ain0 or g2/ain2 input (compsel=0 or 1) to one of the 63 voltage threshold levels. if vloop=1, enables the voltage loop con?uration where the analog g4/ain0 or g2/ain2 input (compsel=0 or 1) to the uncommitted (error) ampli?r output (a out ). bit 7 of the digital delay (ddelay) register is the programmable comparator circuit enable (compen) bit. if compen=0, the programmable comparator circuit is disabled and the c out signal is low. if compen=1, the programmable comparator circuit is enabled and the c out signal generated by the comparison of the two inputs. bit 0 (cout) of the comparator control (comp) register is the latched comparator output (c out ) signal. if the programma- ble comparator circuit is enabled, the c out signal is latched by the main system instruction (f iclk ) clock into the cout bit of the comp register. software may only read the cout bit to monitor the comparator s activity. the cout bit cannot cause any microcontroller hardware interrupt or any other actions. figure 9. programmable comparator block diagram (vloop = 1) v ref 0.23r r + _ + _ ach5 vloop g7/a out g6/-a in programmable reference c out comp register uncommitted (error) amplifier digital delay circuit 3 2 1 0 pwmoff (wken[6]) dd[3] dd[2] dd[1] dd[0] ddelay register f rclk2 5 epwm en comparator compsel (adcntrl2[6]) g4/ain0 g2/ain2 fms7401l product specification 30 rev. 1.0.3 1/24/05 5.3 digital delay filter with pwmoff output the programmable comparator s output (c out ) is fed into the digital delay ?ter with a programmable delay time. the c out signal toggles from 0 to 1 when the external input (g4/ain0 or g2/ain2) voltage is higher than the programmed voltage threshold or uncommitted ampli?r output (a out ), depending on the state of vloop. the c out rising edge transition triggers the programmable digital delay counter to begin incrementing. with each digital delay count, its value is compared against the v alue stored in the dd[3:0] bits of the digital delay (ddelay) control register. if c out remains high when the digital delay count equaling dd[3:0] completes, the pwmoff signal transitions from 0 to 1. this rising edge transition of the pwmoff signal is then used to either disable the pwm timer 1 circuit completely or the current pwm cycle forcing the pwm output signals to their resting (off) state. the pwmoff output signal may also be programmed as an input of the g6 port miw circuit. interrupts may be triggered if the g6 port miw circuit is enabled and con?ured to trigger its microcontroller hardwar e interrupt (edgei). refer to the multi-input w ak eup circuit section of the datasheet regarding for con?uration details. bit 7 of the ddelay register is the programmable comparator circuit enable (compen) bit. if compen=0, the program- mable comparator circuit is disabled and the c out signal is low. if compen=1, the programmable comparator circuit is enabled and the c out signal is generated by the comparison of the two inputs. bit 6 (pwmint) of the ddelay register, if set to 1, selects the pwmoff signal in place of its g6 input to the miw circuit. software must then enable the miw pwmoff/g6 circuit by setting the wken[6] bit. the wkedg[6] bit must also be cleared to select the rising edge transitions on the pwmoff signal as its wkpnd[6] bit trigger. software may monitor the wkpnd[6] ?g or enable the miw hardware interrupt (edgei) to help detect when the pwmoff signal is triggered. 3 bit 5 (epwm) of the ddelay register is the digital delay ?ter and pwmoff signal enable bit. the epwm bit is active low so that on power-up (after a system reset) the digital delay ?ter circuit is automatically enabled once the programmable comparator circuit is enabled. if the programmable comparator and pwm timer 1 circuits are enabled, since the ?ter is defaulted enabled, the pwmoff signal may disable the pwm timer 1 upon a comparator transition. if the digital delay ?ter and pwmoff circuit is not needed, software must set the epwm bit to 1 disabling the ?ter before enabling the programma- ble comparator to prevent unwanted disables of the pwm timer 1 circuit or its outputs. bit 4 (offmode) of the ddelay register determines how the pwmoff signal affects the pwm timer 1 circuit. if off- mode=0 and the timer 1 circuit is con?ured in an enabled pwm mode, timer 1 is automatically disabled forcing the pwm t1hs1 and t1hs2 output signals to their resting (off) states with the rising edge of the pwmoff signal. the t1c0 bit of the t1cntrl2 register is cleared, reinitializing the 12-bit tmr1 counter to 0x000. software must re-enable the timer 1 circuit to reactivate the pwm output signals. if offmode=1 and timer 1 is con?ured in pwm mode, the t1hs1 and t1hs2 output signals are forced to their resting (off) state until the current pwm cycle completes. once the pwm cycle completes, the pwmoff signal releases the t1hs1 and t1hs2 output signals and they resume with their normal operation even if the c out signal remains active (1). the next pwmoff trigger will not occur until the next rising edge of c out . bits 3-0 (dd[3:0]) of the ddelay register determine how long to delay the trigger of the pwmoff signal once the rising edge of c out has been detected. once the digital delay counter is triggered, the delay count is compared against the value stored in the dd[3:0] bits. once the delay counter completes its dd[3:0] count, if c out remains high, the pwmoff signal is triggered. the digital delay counters increment at the device reference clock rate (f rclk2 ). 4 product specification fms7401l rev. 1.0.3 1/24/05 31 ta b le 11. digital delay (ddelay) register bit de?itions figure 10. digital delay timing 1. refer to the adc circuit section of the datasheet for additional details. 2. refer to the i/o ports section of the datasheet for details. 3. hardware interrupts are not executed by the microcontroller core unless the global interrupt enable (g) flag of the status re gister is set. refer to the 8-bit microcontroller core section of the datasheet for details. 4. refer to the clock circuit section of the datasheet for details regarding the f rclk2 clock. ddelay register (addr. 0xa2) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 compen pwmint epwm offmode dd[3:0] bit description compen (0) disable the programmable comparator circuit. (1) enable the programmable comparator circuit. pwmint (0) the input of the g6 miw circuit network is the g6/-a in device pin. (1) the input of the g6 miw circuit network is the pwmoff output signal (not the g6/-a in device pin). epwm (0) enables the digital delay filter circuit. the pwmoff output is triggered by c out after the programmed delay (t ddelay ). (1) disables the digital delay filter circuit and the pwmoff output signal. offmode (0) pwm outputs switched off and timer 1 stops after a comparator detection with delay. (1) pwm outputs switched off for the current pwm cycle only. dd[3:0] digital delay after c out triggers high, t ddelay = dd ?(1/f rclk2 ) t ddelay start sample comparator output digital delay pwmoff t1hs1 t1hs2 fms7401l product specification 32 rev. 1.0.3 1/24/05 6 pwm timer 1 circuit the pulse width modulation (pwm) timer 1 circuit, a programmable 12-bit pwm timer with a 3-bit prescaler can be con?- ured to operate in both pwm and input capture modes. in pwm mode, the timer 1 circuit may be con?ured to generate pulses of a speci?d duty cycle and period on the t1hs1 (g0), t1hs2 (g5), and/or adstrobe (g1) timer output ports. on the other hand, in input capture mode, the timer 1 circuit may be con?ured to capture and store the current timer value at the time of a trigger de?ed by the rising or falling edge of the t1hs2 (g5) input port. in addition, the t1hs1 and adstrobe pwm outputs may be generated as in the pwm mode. the timer 1 circuit backbone is a 12-bit programmable up-counter (tmr1) that is accessible by software, with read-only access, through the 4-bit tmr1hi and 8-bit tmr1lo memory mapped registers where tmr1={tmr1hi, tmr1lo}. 1 upon a system reset or once entering a new timer 1 mode of operation, the 12-bit tmr1 counter is initialized to 0x000. once a selected timer 1 mode is enabled, the tmr1 counter will begin incrementing by the f t1clk clock with the programmed divide f actor de?ed by a 3-bit prescaler. once the tmr1 over?ws, tmr1 is reinitialized to 0x000 and resumes incrementing until software disables the mode. in pwm mode, the tmr1 over?w value may be programmed by software where, in input capture mode, the tmr1 will over?w once the 0xfff count completes. the timer 1 circuit may be programmed to generate microcontroller hardware interrupts with every tmr1 over?w and capture. the timer 1 f t1clk clock may be programmed to operate from high to low frequencies with the use of the programmable digital clock multiplier (pll) and internal oscillator in order to provide the maximum ?xibility for various pwm applica- tions. 6.1 pwm timer 1 con?uration registers software must access the six memory mapped pwm timer 1 registers to con?ure and control the timer 1 circuit. 1 the 8-bit prescale (pscale) register is used to con?ure the entire fms7401l clock structure including the timer 1 s f t1clk . the 12- bit timer 1 compare a (t1cmpa), timer 1 compare b (t1cmpb), and timer 1 reload (t1ra) registers are used to de?e the pwm output signal s duty cycle and period. the 5-bit dead time (dtime) register is used to de?e the time delay (t dt ) between the pwm t1hs1 and t1hs2 edge transitions while in pwm mode. the timer 1 control (t1cntrl) register is used to select timer 1 s operating mode, enable its pwm output signals, and control its hardware interrupt (tmri1). 6.1.1 pscale register and timer 1 clock configuration although the pscale register is part of the pwm timer 1 circuit, its register bits con?ure the clock structure for the entire fms7401l along with the timer 1 clock (f t1clk ). refer to the clock circuit section of the datasheet for details regarding the device s clock structure. the f t1clk source may be supplied by either the programmable f pwmclk pll output or the main instruction (f iclk ) clock. once the f t1clk source is selected, it may not be changed while the timer 1 circuit is in pwm mode and running or in input capture mode (run mode). upon a system reset, the pscale register is automatically initialized to 0x00. bit 7 of the pscale register is the pll circuit enable (pllen) bit. before using any of the pll outputs, software must enable the pll circuit and wait the t pll_lock to ensure that the pll is locked into its appropriate frequency and in phase. the pllen bit may not be changed while the timer 1 circuit is in run mode. any attempts to write to pllen under this condition will be ignored and its value will remain unchanged. bits 6 and 5 (fs[1:0]) of the pscale register are the bits used to select between the different output frequencies available to the pll s f pwmclk output signal. fs selects between the four available pll divide factors (divide-by-1/2/4/8) selecting an out- put frequency of 8/16/32/64mhz (see t able 13 ). the fs bits may be changed by software at any time; however, if the timer 1 circuit is in run mode, the fs value will not change the f pwmclk output frequency until after the tmr1 counter over?ws end- ing the current pwm cycle. the last fs value at the tmr1 counter over?w will dictate the divide factor of the f pwmclk out- put for the next pwm cycle. when reading fs, the value reported will be the last value written by software and may not necessarily re?ct the divide factor for the current pwm cycle. product specification fms7401l rev. 1.0.3 1/24/05 33 bit 4 of the pscale register is the frequency selection (fsel) bit for the timer 1 circuit. fsel is used to select between the slow or high frequency options, ultimately selecting the f t1clk to be sourced either by the f iclk or f pwmclk (see t able 13 ). if fsel=0, the slow frequency option is selected and the f iclk will then source the f t1clk with either a 1/8mhz frequency determined by the fmode bit, as discussed later in the section. if fsel=1, the high frequency option is selected and the f pwmclk will then source the f t1clk at a frequency selected by the fs[1:0] bits. the fsel bit may not be set if the pll is not enabled (pllen=0) or changed while the timer 1 circuit is in run mode. any attempts to write to fsel under this condition will be ignored and its value will remain unchanged. bit 3 (fmode) of the pscale register is the frequency selection bit for the main instruction clock (f iclk ). fmode is used to select between the slow or high frequency options, ultimately selecting the f iclk to be sourced either by the internal oscilla- tor (or the external digital clock) operating at f osc 2 or the pll s f (fs=0) output signal. 3 if fmode=0, the slow frequency option is selected and the internal oscillator will then source the f iclk at a f osc /2 frequency. if fmode=1, the high frequency option is selected and the f (fs=0) will then source the f iclk with pll s divide-by-8 output frequency. with the fmode bit enabled, it is possible to execute instructions at a speed approximately eight times faster than the standard. the fmode bit may not be set if the pll is not enabled (pllen=0). any attempts to write to fmode while pllen=0 will force fmode=0 ignoring any set instructions. once the pll has been enabled, software may change f iclk ? clock source on-the-? during normal instruction execution in order to speed-up a particular action. bits 2-0 of the pscale register are the three prescaler (ps[2:0]) bits used to divide the f t1clk to obtain a wider frequency range on the pwm output signals (see t able 14 ). the ps bits are used by the timer 1 circuit to increment the 12-bit tmr1 at a frequency equal to f t1clk divided-by 1 through 8. the ps bits (like fs) may be changed by software at any time; however, if the timer 1 circuit is in run mode, the ps value will not change the prescale division factor until after the tmr1 counter over - ?ws ending the current pwm cycle. the last ps value at the tmr1 counter over?w will dictate the prescale divide factor of the f t1clk for the next pwm cycle. when reading ps, the value reported will be the last value written by software and may not necessarily re?ct the divide factor for the current pwm cycle. ta b le 12. prescale (pscale) register bit de?itions ta b le 13. pll divide factor selection bits and the f t1clk resolution (f osc =2 mhz) pscale register (addr. 0xa4) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pllen fs[1:0] fsel fmode ps[2:0] bit description pllen (0) disables the pll circuit. (1) enables the pll circuit. fs[1:0] pll divide factor selection bits. refer to table 13 for details. fsel (0) selects f iclk as timer 1? clock (f t1clk ) source. (1) selects f pwmclk pll output as timer 1? clock (f t1clk ) source. fmode (0) selects f clk divided-by-2 output as the main system instruction clock (f iclk ) source. (1) selects f (fs=0) pll output as the main system instruction clock (f iclk ) source. ps[2:0] timer 1 prescale selection bits. refer to table 13 for details. fs[1:0] f pwmclk f t1clk (fsel=0) f t1clk (fsel=1) max pwm freq. (8-bit resolution) max pwm freq. (12-bit resolution) fmode=0 fmode=1 fsel=0 fmode=0 fsel=1 fsel=0 fmode=0 fsel=1 00 8 mhz 1 mhz 8 mhz 8 mhz 3.906 khz 31.25 khz 244.14 hz 1.95 khz 01 16 mhz 1 mhz 8 mhz 16 mhz 3.906 khz 62.5 khz 244.14 hz 3.9 khz 10 32 mhz 1 mhz 8 mhz 32 mhz 3.906 khz 125 khz 244.14 hz 7.8 khz 11 64 mhz 1 mhz 8 mhz 64 mhz 3.906 khz 250 khz 244.14 hz 15.625 khz fms7401l product specification 34 rev. 1.0.3 1/24/05 ta b le 14. timer 1 prescale selection (ps) bits 6.1.2 pwm cycle configuration registers the pwm timer 1 circuit has three 12-bit (t1cmpa, t1cmpb, t1ra) and one 5-bit (dtime) con?uration registers used to specify the duty cycle and period of the timer 1 output signals. upon a system reset, all four registers are initialized with o nes (0xfff, 0x1f). all con?uration registers must be programmed with their appropriate values prior to enabling the timer 1 circuit. except for the dtime register, the t1cmpa, t1cmpb and t1ra registers may be changed by software at any time; however, if the timer 1 circuit is in run mode, the register values will not change the timer 1 output signal s attributes unti l after the tmr1 counter over?ws ending the current pwm cycle. the last register values at the tmr1 counter over?w will dictate the output signal s attributes for the next pwm cycle. when reading the registers, the value reported will be the last v alue written by software and may not necessarily re?ct the output signal s attributes for the current pwm cycle. the 12-bit t1ra is timer 1 s reload/capture register (depending on the selected operating mode). all 12 bits are accessible by software through the 4-bit t1rahi and 8-bit t1ralo memory mapped registers where t1ra= {t1rahi, t1ralo}. 1 in pwm mode, t1ra con?ures the period of the t1hs1, t1hs2 and adstrobe outputs and determines after what tmr1 count it will over?w (reinitialize to 0x000) to begin the next pwm cycle. in input capture mode, t1ra contains the captured v alue of the tmr1 count at the time of the trigger de?ed by the rising or falling edge of the t1hs2 input. the 12-bit t1cmpa is timer 1 s compare a register that dictates the length of the resting (off) state of the t1hs1 and t1hs2 output signals. all 12 bits are accessible by software through the 4-bit t1cmpahi and 8-bit t1cmpalo memory mapped registers where t1cmpa={t1cmpahi, t1cmpalo}. 1 in pwm mode, the tmr1 counter is compared against t1cmpa (tmr1=t1cmpa) to determine when the ?st transition of the t1hs1 and t1hs2 output signals should be triggered. in input capture mode, the t1cmpa value is still used to con?ure t1hs1 but has no affect on the t1hs2 signal since it is used as an input of the timer 1 circuit in this mode. software must ensure that the total t1cmpa plus t dt time is not greater than or equal to the total t1ra plus t dt times. the 12-bit t1cmpb is timer 1 s compare b register that dictates the length of the resting (off) state of the adstrobe out- put signal. all 12 bits are accessible by software through the 4-bit t1cmpbhi and 8-bit t1cmpblo memory mapped regis- ters where t1cmpb={t1cmpbhi, t1cmpblo}. 1 the tmr1 counter is compared against t1cmpb to determine when the ?st transition of the adstrobe output signal should be triggered. if enabled, at the rising edge of adstrobe (tmr1=t1cmpb) an analog-to-digital converter (adc) conversion may be initiated. 4 software must ensure that the total t1cmpb plus t dt time is not greater than or equal to the total t1ra plus t dt times. bits 4-0 (dt[4:0]) of the dtime register determines the amount of dead time (t dt ) delay, if any, between the t1hs1 and t1hs2 output signal transitions (see t able 13 ). in pwm mode, once the tmr1 counter equals the t1cmpa value, the t1hs1 signal transitions ending its resting (off) state. the dead time delay counter is then initiated incrementing with each edge of the f t1clk up to the programmed dt[4:0] value. 5 once t dt has passed, the t1hs2 signal will then transition ending its resting (off) state. as the tmr1 counter continues, once the tmr1 counter equals the t1ra value, the t1hs2 signal transitions end- ing its active (on) state. the dead time delay counter is then reinitiated incrementing to the dt[4:0] value. once t dt has passed, the t1hs1 signal will then transition ending its active (on) state. ps[2] ps[1] ps[0] timer 1 clock 00 0 f t1clk / 1 00 1 f t1clk / 2 01 0 f t1clk / 3 01 1 f t1clk / 4 10 0 f t1clk / 5 10 1 f t1clk / 6 11 0 f t1clk / 7 11 1 f t1clk / 8 product specification fms7401l rev. 1.0.3 1/24/05 35 ta b le 15. dead time (dtime) register bit de?itions 6.1.3 timer 1 control register the timer 1 control (t1cntrl) register is used to select timer 1 s operating mode, enable its pwm output signals, and con- trol its hardware interrupt (tmri1). upon a system reset, the t1cntrl register is automatically initialized to 0x00. refer to t able 16 and t able 17 for additional details regarding the t1cntrl register bits. bit 7 (t1c3) of the t1cntrl register selects between the two timer 1 operating modes. if t1c3=0, the timer 1 circuit will be con?ured in pwm mode. once timer 1 is con?ured in pwm mode, the tmr1 counter must be started in order for the circuit to be enabled and considered to be in run mode. if t1c3=1, the timer 1 circuit will be con?ured in input capture mode. once in input capture mode, the timer 1 circuit is immediately enabled and the tmr1 counter will automatically begin incrementing from its initial state (0x000) until timer 1 s operating mode is returned to a disabled pwm mode (its default). therefore, software must issue a write command clearing t1c3 and t1c0 within the same instruction. if t1c3 is cleared while t1c0 is set, the timer 1 circuit will remain in input capture mode until the tmr1 over?ws and t dt completes ending the current pwm cycle. once the tmr1 over?ws, the operating mode is switched to a disable pwm mode even though t1c0=1. software must clear t1c0 before re-enabling the timer 1 circuit in any of the two operating modes. bit 6 (t1c2) of the t1cntrl register has two functions depending on timer 1 s selected operating mode. in pwm mode, t1c2 is used to enable the t1hs2 (g5) output signal (if set). otherwise, the t1c2 bit (if zero) disables the t1hs2 output sig- nal. the t1hs2 signal on the g5 pin may be con?ured as an active high or low output depending on the con?ured portgd con?uration. if portgd[5]=0, the t1hs2 (g5) output is active high, otherwise it is active low. in input capture mode, t1c2 is used to select the edge to trigger a tmr1 t1hs2 input capture. if t1c2=0, every rising edge of the t1hs2 input will trigger a tmr1 capture. if t1c2=1, every falling edge will trigger a capture. software may change the value of t1c2 at any time; however, if the circuit is in run mode, t1c2 will not change the circuit s attribute until after the tmr1 counter over?w s and the t dt passes completing the current pwm cycle. the last t1c2 value after the t dt completes, will dictate the circuit s attribute for the next pwm cycle. when reading the t1c2, the value reported will be the last value written by software and may not necessarily re?ct the circuit s attribute for the current pwm cycle. bit 5 (t1c1) of the t1cntrl register enables or disable the t1hs1 (g0) output signal for either operating mode. if t1c1=1, the t1hs1 output signal is enabled, otherwise it is disabled. the t1hs1 signal on the g0 pin may be con?ured as an active high or low output depending on the con?ured portgd con?uration. if portgd[0]=0, the t1hs1 (g0) output is active high, otherwise it is active low. software may change the value of t1c1 at any time; however, if the circuit is in run mode, t1c1 will not change the circuit s attribute until after the tmr1 counter over?ws and the t dt passes completing the current pwm cycle. the last t1c1 value after the t dt completes, will dictate the circuit s attribute for the next pwm cycle. when reading the t1c1, the value reported will be the last value written by software and may not necessarily re?ct the circuit s attribute for the current pwm cycle. the adstrobe signal is outputted through the device s g1 pin when bit 0 (t1bout) of the t1cntrl register is set to 1. the adstrobe output is always generated by the timer 1 circuit regardless of the state of t1bout. the adstrobe signal on the g1 pin may be con?ured as an active high or low output depending on the con?ured portgd con?uration. if portgd[1]=0, the adstrobe (g1) output is active high, otherwise it is active low. software may change the value of t1bout at any time; however, if the circuit is in run mode, t1bout will not change the device s i/o attribute until after the tmr1 counter over?ws and the t dt passes completing the current pwm cycle. the last t1bout value after the t dt com- dtime register (addr. 0xa5) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xx x dt[4:0] dt[4:0] dead time delay (t dt ) 0x00 no dead time delay 0x01 ?0x1f (1/f t1clk ) ?dt fms7401l product specification 36 rev. 1.0.3 1/24/05 pletes, will dictate the device s i/o attribute for the next pwm cycle. when reading the t1bout, the value reported will be the last value written by software and may not necessarily re?ct the device s i/o attribute for the current pwm cycle. bit 4 (t1c0) of the t1cntrl register has two functions depending on timer 1 s selected operating mode. in pwm mode, when t1c0=1, the tmr1 circuit becomes enabled and begins to increment from its initial 0x000 state; otherwise, the tmr1 counter is stopped and reinitialized. software may disable the timer 1 circuit at any time; however, the tmr1 counter and pwm outputs will not be disabled until the current pwm cycle completes. software should monitor the t1c0 bit to determine when the pwm cycle ends and timer 1 circuit actually disabled. in input capture mode, the t1c0 bit is one of the tmr1 ov er?w (a transition from 0xfff to 0x000) pending ?gs used to trigger the timer 1 circuit s hardware interrupt if the inter- rupt is enabled. in order for software to properly monitor the tmr1 over?ws, the t1c0 bit must be cleared before the next tmr1 over?w. bit 3 (t1pnd) of the t1cntrl register has two functions depending on timer 1 s selected operating mode. in either operat- ing modes, the t1pnd bit is one of the timer 1 circuit s hardware interrupt pending ?gs if the interrupt is enabled. in pwm mode, the t1pnd bit is triggered by a tmr1 over?w (a transition from the t1ra count to 0x000). however, in input cap- ture mode, the t1pnd bit is triggered by the capture of the current tmr1 value by the rising or falling edge of the t1hs2 (g5) input port. in order for software to properly monitor the pending ?g, the t1pnd bit must be cleared before the next tmr1 over?w or capture. bit 2 of the t1cntrl register is the timer 1 s microcontroller hardware interrupt enable (t1en) bit. if set, hardware inter- rupts are enabled and trigger by the t1pnd and/or t1c0 pending ?gs depending on timer 1 s operating mode. 6 if in pwm mode, the hardware interrupt is triggered only by the t1pnd bit. if in input capture mode, the t1pnd and t1c0 bits are log- ically-ored together. as long as a timer 1 pending ?g is set, the hardware interrupt will continue to execute software s timer 1 interrupt service routine until the pending ?g is cleared. 7 the sbit or rbit instructions may be used to either set or clear one of the t1cntrl register bits, like the t1en bit. the sbit and rbit instructions both take two instruction clock cycles to complete their execution. in the ?st cycle, all register bits are automatically read to obtain their most current value. in the second cycle, the bit to be set/cleared is given its new v alue and all bits are then re-written to the register. using the sbit/rbit instruction to set/clear an enable bit with a pending ?g in the same register may cause a potential hazard. software may inadvertently clear a recently triggered pending ?g if the trigge r happened during the second phase of the sbit/rbit instruction execution. to avoid this condition, the ld instruction must be used to set or clear the interrupt enable bits. the timer 1 circuit is designed such that software may not trigger a pending ? g by writing a 1 to the t1pnd and t1c0 (if in input capture mode) bits, they may only be cleared. the action of writing a 1 to a t1pnd and t1c0 register bits holds the current bit values. the action of writing a 0 to the t1pnd and t1c0 register bits clears the bit values. therefore, if timer 1 is con?ured for a rising edge triggered input capture mode with outputs enabled and software is to enable interrupts without interrupting the pending ?gs, the ?d t1cntrl, #0bdh?instruction should be used. the t1en bit will be set to 1 without clearing t1pnd and/or t1c0. product specification fms7401l rev. 1.0.3 1/24/05 37 ta b le 16. timer 1 control (t1cntrl) register bit de?itions ta b le 17. timer 1 mode con?uration bits 6.2 pulse width modulation (pwm) mode in pwm mode, the timer 1 circuit may be con?ured to generate pulses of a speci?d duty cycle and period on the t1hs1 (g0), t1hs2 (g5), and/or adstrobe (g1) timer outputs. the 12-bit tmr1 counter increments at the f t1clk clock rate de?ed by the fsel bit of the pscale register. refer to the previous pscale re gister and t imer 1 clock con guration section of the datasheet for details. a pwm cycle begins with the tmr1 counter incrementing from 0x000 until it matches the value stored in the t1ra register. at this point, the tmr1 counter completes its t1ra count and over?ws (a transitions from t1ra to 0x000) setting the t1pnd ?g of the t1cntrl register ending the pwm cycle. the timer 1 circuit has two additional tmr1 compare (t1cmpa and t1cmpb) registers used to generate the t1hs1, t1hs2, and adstrobe output signals. all three output signals are initialized to a resting (off) state. once the tmr1 counter is enabled (by setting the t1c0 bit of the t1cntrl register), both compare registers are matched against the incrementing tmr1 counter. when the tmr1 completes its count equal to the value stored in the t1cmpa and t1cmpb registers, the t1hs1, t1hs2, and adstrobe output signals are set to an active (on) state until the tmr1 counter matches the value stored in the t1ra compare register (over?ws). once the tmr1 counter over?ws, the output signals are cleared returning them to a resting (off) state. refer to figure 11 for a timer 1 pwm mode block diagram. t1cntrl register (addr. 0xae) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t1c3 t1c2 t1c1 t1c0 t1pnd t1en x t1bout bit description t1c3 timer 1 mode configuration bit. refer to table 17 for details. t1c2 timer 1 mode configuration bit. refer to table 17 for details. t1c1 timer 1 mode configuration bit. refer to table 17 for details. t1c0 pwm mode (0) stop the pwm timer 1 circuit. (1) start the pwm timer 1 circuit. input capture mode (0) timer 1? tmr1 overflow pending flag is cleared. (1) timer 1? tmr1 overflow pending flag is triggered. t1pnd pwm mode (0) timer 1? tmr1 overflow pending flag is cleared. (1) timer 1? tmr1 overflow pending flag is triggered. input capture mode (0) timer 1 capture pending flag is cleared. (1) timer 1 capture pending flag is triggered. t1en (0) disables timer 1 hardware interrupts. (1) enables timer 1 hardware interrupts. t1bout (0) retain normal i/o function of the g1/ain3 pin. (1) enables timer 1? adstrobe output to be sent to the g1 output port. t1c3 t1c2 t1c1 timer mode source interrupt timer count on 00 0 pwm mode no output toggle tmr1 over?w prescaler input 01 1 pwm mode t1hs1 and t1hs2 toggle tmr1 over?w prescaler input 00 1 pwm mode t1hs1 toggle tmr1 over?w prescaler input 01 0 pwm mode t1hs2 toggle tmr1 over?w prescaler input 10 0 capture mode no t1hs1 toggle tmr1 over?w t1hs2 rising-edge prescaler input 10 1 capture mode with t1hs1 toggle tmr1 over?w t1hs2 rising-edge prescaler input 11 0 capture mode no t1hs1 toggle tmr1 over?w t1hs2 falling-edge prescaler input 11 1 capture mode with t1hs1 toggle tmr1 over?w t1hs2 falling-edge prescaler input fms7401l product specification 38 rev. 1.0.3 1/24/05 the pwm timer 1 can be programmed to toggle one or both pwm output signals (t1hs1 and t1hs2) to support a variety of output con?urations (half bridge, full bridge, 8 low side or high side driving). these outputs may be used to drive an external half-bridge driver and are enabled by programming the t1c1 and t1c2 bits in the t1cntrl register (see t able 16 ). the t1hs1 (g0) and t1hs2 (g5) output signals may be con?ured with opposite phases and dead time controlled edges (see figure 12 ). the phases of the output signals are con?ured by the bits of the portgd i/o con?uration register. 9 upon device power-up, the t1hs1 and t1hs2 signals may be programmed to default as active high/low outputs by the default i/o con?u- ration register bits in the non-volatile initialization register 4. 10 both g0/t1hs1 and g5/t1hs2 pins will con?ure to their programmed default state after t dio 2 from the system reset trigger (e.g. from a por). the g0/t1hs1 and g5/t1hs2 pins may both be con?ured as outputs with common or opposite phases. if con?ured as outputs, the portgd[0] and portgd[5] bits con?ure the t1hs1 and t1hs2 signals as active high or low. if the portgd bit is 0, the output signal is active high, other- wise it is active low. the portgd[1] bit also con?ures the g1/adstrobe pin as an active high/low signal once con?ured as an output. the initialization register 4 bits only default the g0/t1hs1 and g5/t1hs2 pins not the g1/adstrobe pin. from factory, the g0/t1hs1, g5/t1hs2 and g1/adstrobe device pins are defaulted as tri-stated inputs. the pins must be con?ured by the initialization register 4 bits or by software directly through the portgc and portgd register as an output port before enabling the tmr1 counter and its outputs. the dead time counter of the timer 1 circuit controls the dead time (t dt ) delay between the t1hs1 and t1hs2 output edge transitions through the dt[4:0] bits of the dtime register. the dead time counter delay is ?st triggered after the tmr1 counter equals to the t1cmpa value and the t1hs1 signal transitions from its resting (off) to its active (on) state. once the programmed t dt completes, the t1hs2 signal then transitions from its resting (off) to its active (on) state. the dead time counter delay is triggered for a second time after the tmr1 counter equals to the t1ra value and the t1hs2 signal transitions from its active (on) to its resting (off) state. once the programmed t dt completes, the t1hs1 signal then transitions from its active (on) to its resting (off) state ending the pwm cycle. the pwm cycle is considered complete once the tmr1 counter completes the t1ra count plus t dt even in the t1hs1 and t1hs2 outputs are disabled. the t1hs1 and t1hs2 pwm output signals may be programmed to be automatically disabled by the output of the digital ?ter (pwmoff) in programmable comparator circuit. the output may be programmed to disable the timer 1 circuit completely or disable only the current pwm cycle. refer to the programmable comparator circuit section of the datasheet for details. the timer 1 s adstrobe output signal may be con?ured as the g1/adstrobe device output if the t1bout bit of the t1cntrl register is set. the adstrobe signal, however, is always generated by the timer 1 circuit. initially, the adstrobe begins its pwm cycle at its resting (off) state and transitions to its active (on) state once the tmr1 counter com- pletes its count equal to the t1cmpb value. the active (on) edge transition of the adstrobe output may be programmed to automatically trigger an adc conversion cycle if the endas bit of the adcntrl2 register is set. refer to the adc circuit section of the datasheet for details. the t1pnd bit of the t1cntrl register is set once the tmr1 counter completes the count equal to the t1ra value (over- ?ws). software may use the t1pnd bit to monitor the pwm cycles and/or trigger microcontroller hardware interrupts (tmri1) if the t1en bit of the t1cntrl register is set. software must clear the t1pnd bit in order to detect a new over?w condition and/or trigger a new interrupt. 6 product specification fms7401l rev. 1.0.3 1/24/05 39 figure 11. timer 1? pwm mode block diagram figure 12. example pwm output signals a) and b) tmr1 dead time control portgd pwmoff t1hs1/g0 f t1clk 5 12 ps2 ps1 ps0 pscale 2 1 1 0 t1hs2/g5 t1cmpa tmr1=t1cmpb endas adstrobe 12 g1/ain3 5 t1cmpb [11:0] tmr1=t1cmpa [11:0] clock divider fin fout [11:0] t1bout dtime dt[4:0] t1ra [11:0] t1pnd t dt t dt t dt t pwm t1hs1 t1hs2 0xfff 0x00 t1cmpa t1ra t1cmpb t dt t dt t1hs1 t1hs2 adstrobe sample & hold adc conversion adc block t dt t dt sample & hold adc conversion sample & hold adc conversion sample & hold adc conversion t smp t conv a) b) fms7401l product specification 40 rev. 1.0.3 1/24/05 6.3 input capture mode when the pwm timer 1 circuit is con?ured in input capture mode, the t1hs2 signal is used as an input of the timer 1 circuit instead of an output as in pwm mode. the g5/t1hs2 device pin should be con?ured by software as an input port. the timer 1 circuit may be programmed to capture the tmr1 counter value in the t1ra register with every rising or falling edge transition of the t1hs2 input. with each tmr1 capture, the t1pnd bit of the t1cntrl register is set. for synchroniza- tion purposes, the t1hs2 input is synchronized with the f t1clk clock before being allowed to trigger a tmr1 capture. a max- imum of three f t1clk cycle tmr1 capture delay will occur with each edge transition on the g5/t1hs2 device pin. once the timer 1 circuit is con?ured for input capture mode, the tmr1 counter starts incrementing continuously from 0x000 through 0xfff until the timer 1 is returned to a disabled pwm operating mode. once the tmr1 counter over?ws (transitions from 0xfff to 0x000) the t1c0 pending bit on through t1cntrl register is set. in input capture mode, it is still possible to generate output signals with variable duty-cycle thanks to the t1cmpa and t1cmpb compare registers. if enabled, the t1hs1 and adstrobe output signals may be generated as in pwm mode. refer to the previous pulse w idth modulation (pwm) mode section of the datasheet for details. figure 13. timer 1? input capture mode block diagram 1. refer to table 30 of the device memory section of the datasheet for the detailed memory map. 2. refer to the electrical characteristics section of the datasheet. 3. the pll? (f (fs=0) ) output is not affected by the fs[1:0] bit value of the pscale register and merely shares the fs[1:0]=00 divide factor. 4. refer to the adc circuit section of the datasheet for additional details. 5. the three ps bits have no affect on the dead time, only the tmr1 counter. 6. hardware interrupts are not executed by the microcontroller core unless the global interrupt enable (g) flag of the status re gister is set. refer to the 8-bit micro- controller core section of the datasheet for details. 7. the timer 1 hardware interrupt will be executed in the defined priority order. refer to the 8-bit microcontroller core section of the datasheet for details. 8. the full bridge requires two additional output ports to complete the bridge configuration. 9. refer to the i/o ports section of the datasheet for additional details. 10.refer to the device memory section of the datasheet for details regarding the initialization registers. t1ra tmr1 portgd g0/t1hs1 f t1clk 12 clock divider ps2 ps1 ps0 pscale [11:0] 1 t1cmpa tmr1=t1cmpb endas adstrobe 12 g1/ain3 0 t1cmpb [11:0] tmr1=t1cmpa [11:0] t1c0 edge control t1c2 t1pnd fin fout [11:0] t1bout g5/t1hs2 product specification fms7401l rev. 1.0.3 1/24/05 41 7 timer 0 circuit t imer 0 s main circuit is a 12-bit free running up-counter whose clock source is the main system instruction clock (f iclk ). the main counter may be used to generate microcontroller hardware interrupts and serve as a prescaler for the idle and watchdog t imers. after power-up or any system reset, the timer 0 s 12-bit counter is initialized to 0x000 and continuously increments with each instruction clock. the 12-bit counter is not memory mapped; therefore, software cannot read or write to the counter registers. however, software may monitor the timer 0 s main counter by reading the state of the timer 0 pending (t0pnd) bit of the t imer 0 control (t0cntrl) memory mapped register. 1 the t0pnd ?g is automatically set with each counter over?w (a transition from 0xfff to 0x000) which occurs after every 4,096 cycles. at every over?w, the counter rolls over to 0x000 and continues to increment. in order for software to properly monitor the main counter, the t0pnd bit must be cleared before the next counter over?w. the t0cntrl register houses two hardware interrupt enable bits. the wkinten register bit is the miw hardware interrupt enable bit. for details regarding its usage refer to the multi-input w ak eup circuit section of the datasheet. the t0inten register bit is timer 0 s microcontroller hardware interrupt (tmri0) enable bit. if set, hardware interrupts are enabled and trigger by the t0pnd ?g. 2 as long as a timer 0 pending ?g is set, the hardware interrupt will continue to execute software s t imer 0 interrupt service routine until the pending ?g is cleared. 3 the sbit or rbit instructions may be used to either set or clear the t0inten or wkinten bits. the sbit and rbit instructions both take two instruction clock cycles to complete their execution. in the ?st cycle, all register bits are autom ati- cally read to obtain their most current value. in the second cycle, the bit to be set/cleared is given its new value and all bi ts are then re-written to the register. using the sbit/rbit instruction to set/clear an enable bit with a pending ?g in the same regi s- ter may cause a potential hazard. software may inadvertently clear a recently triggered pending ?g if the trigger happened during the second phase of the sbit/rbit instruction execution. to avoid this condition, the ld instruction must be used to set or clear the interrupt enable bits. the timer 0 circuit is designed such that software may not trigger a pending ?g by wri t- ing a 1 to a t0pnd register bit, it may only be cleared. the action of writing a 1 to a t0pnd register bit holds the current bi t v alue. the action of writing a 0 to a t0pnd register bit clears the bit value. therefore, the ?d t0cntrl, #083h?instruction will set both interrupt enable bits without clearing t0pnd. ta b le 18. timer 0 control (t0cntrl) register de?itions 4 7.1 idle timer once the device enters idle mode, the microcontroller core and other main circuits are disabled for current conservation. the idle timer will automatically wake the device from idle mode, if the miw has not already done so, after a maximum of 8,192 c ycles. 5 the idle timer is a 1-bit extension of the timer 0 s main 12-bit up-counter. with each over?w of the main counter, the idle t imer extension bit is toggled essentially causing the idle timer over?w to occur after 8,192 cycles. once the idle timer ov er?w ?g is triggered, the device wakes from idle mode and starts its instruction execution with the next clock cycle. the idle timer over?w ?g cannot be monitored by software. therefore, in order to maximize the time that the device remains in idle mode software must monitor the t0pnd ?g. once the t0pnd ?g is triggered, software may then issue the idle mode command. software may also loop on the idle mode command to extend the average time the device remains in idle mode, thereby reducing the overall current consumption. 7.2 watchdog timer the watchdog timer is used to safely recover the device in the rare event of a processor ?unaway condition?by issuing a sys- tem reset. a watchdog timer runs continuously with timer 0 s main 12-bit up-counter; however, a watchdog reset will not t0cntrl register (addr. 0xb6) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wkinten x x x x x t0pnd t0inten fms7401l product specification 42 rev. 1.0.3 1/24/05 issue a system reset unless the feature is enabled by the watchdog enable (wden) bit of the initialization register 1. 6 the wden bit can only be set while the device is in programming mode. 7 if set, the watchdog timer s system reset ability will always power-up enabled. software cannot disable watchdog resets. the watchdog reset can only be disabled in program- ming mode by clearing the wden bit as long as the memory write protect (wdis) feature is not enabled. the watchdog timer is a 4-bit extension of the timer 0 s main 12-bit up-counter. with each over?w of the main counter, the w atchdog timer extension bits may increment to a count of 16. if the watchdog timer is allowed to increment to the 16 th count, a watchdog reset is issued triggering a system reset. the system reset will initialize all device circuits and instructi on ex ecution will restart at the default program counter address (0xc00) after t reset delay. 8 in order to service the watchdog timer to prevent a reset, software must write 0x1b to the watchdog service register (wdsvr) before every 61,440 cycles (the 16 th w atchdog timer count) and not earlier than the ?st 4,096 cycles (the 1 st w atchdog timer count) since the last watchdog timer service or system reset. once the watchdog timer is serviced, the 4-bit w atchdog timer is cleared and then continues to increment. the watchdog timer will issue a reset if it is serviced too fre- quently or not frequently enough where the servicing of the watchdog timer is controlled completely by software. the watchdog timer, like timer 0 s counter, is not memory mapped and cannot be accessed by software. software must monitor the watchdog timer by keeping a count of the number of t0pnd ?gs since the last service or reset. if software clears the t0pnd ?gs before the next timer 0 counter over?w, software may count the number of triggered t0pnd ?gs in order to determine when to next service the watchdog timer. the watchdog timer remains operational during idle mode; therefore, software should service the watchdog timer prior to entering idle mode to prevent false resets. it is not recommended to service the watchdog timer within an interrupt service routine (isr). for example, the most obvious place to issue the watchdog service command seems to be within the timer 0 isr since it guarantees the watchdog timer ser- vice to occur within the allowed 4,096-61,440 cycle window. however, this action takes place automatically since the timer 0 circuit runs independently from the microcontroller program execution without knowledge of the state of the microcontroller core. if the program execution is stuck in an in?ite loop due to some unforeseen circumstances, the tmri0 hardware interrupt will still be triggered executing software s isr, the watchdog timer will then be serviced, and program execution will return t o the in?ite loop once the isr completes. the in?ite loop or ?unaway condition?will continue undetected defeating the pur- pose of the watchdog reset feature. the isrs may be used to keep track of the number of cycles since the last watchdog ser- vice (e.g. keep a count of the number of t0pnd ?gs triggered). however, the actual watchdog service command must be issued within software s main program code. ta b le 19. watchdog service register (wdsvr) de?ition 1. refer to table 30 of the device memory section of the datasheet for the detailed memory map. 2. hardware interrupts are not executed by the microcontroller core unless the global interrupt enable (g) flag of the status re gister is set. refer to the 8-bit micro- controller core section of the datasheet for details. 3. the timer 0 hardware interrupt will be executed in the defined priority order. refer to the 8-bit microcontroller core section of the datasheet for details. 4. after a system reset, the t0cntrl register is defaulted to 0x00. 5. refer to the power saving modes section of the datasheet for idle mode wakeup conditions. 6. refer to the device memory section of the datasheet for details regarding the initialization registers. 7. the fms7401l must be placed in a special programming mode in order to have full write and read access of all of the device me mories. refer to the in-circuit programming specification section of the datasheet for details. 8. refer to the electrical characteristics section of the datasheet for details. wdsvr (addr. 0xb5) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 01 1 011 product specification fms7401l rev. 1.0.3 1/24/05 43 8 i/o ports the eight i/o pins (six on the 8-pin package option) are bi-directional (see figure 14 ). the bi-directional i/o pins can be indi- vidually con?ured by software to operate as high-impedance inputs, as inputs with weak pull-up, or as push-pull outputs. the operating state is determined by the contents of the corresponding bits in the data and con?uration registers. each bi-direc- tional i/o pin can be used for general purpose i/o, or in some cases, for a speci? alternate function determined by the on-chi p hardware. figure 14. portgd logic diagram 8.1 i/o registers the i/o pins (g0?7) have three memory mapped port registers associated with the i/o circuitry: a port con?uration (portgc), port data (portgd) and port input (portgp) register. 1 portgc is used to con?ure the pins as inputs or out- puts. a pin may be con?ured as an input by writing a 0 or as an output by writing a 1 to its corresponding portgc bit. if a pin is con?ured as an output, its portgd bit represents the state of the pin (1 = logic high, 0 = logic low). if the pin is co n- ?ured as an input, its portgd bit selects whether the pin is a weak pull-up or a high-impedance input. t able 20 provides details of the port con?uration options. the port con?uration and data registers can both be read from or written to. reading portgp returns the value of the port pins regardless of how the pins are con?ured. since this device supports miw, all input ports have schmitt triggers. upon power-up, the portgc and portgd registers are initialized to 0x00. however, the g0/t1hs1 and g5/t1hs2 pins may be defaulted to the different i/o con?urations de?ed by the default i/o con?uration bits of the initialization register 4. refer to t able 29 in the de vice memory section of the datasheet for details. ta b le 20. i/o register bit assignments ta b le 21. i/o con?uration options 1. refer to table 30 of the device memory section of the datasheet for the detailed memory map. 2. available only on the 14-pin package option. portgc, portgd, portgd registers (addr. 0xb3, 0xb2, 0xb4) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 g7 2 g6 2 g5 g4 g3 g2 g1 g0 portgc bit portgd bit po rt pin con?uration 00 high-impedance input (tri-state input) 01 input with pull-up (weak one input) 10 push-pull zero output 11 push-pull one output gx gxin gxout gxpullen gxbufen product specification fms7401l rev. 1.0.3 1/24/05 44 9 multi-input wakeup circuit the multi-input wakeup (miw) circuit may be used to wake the device from either halt or idle mode 1 with an external event, generate ?gs for software monitoring and microcontroller hardware interrupts by any one or all i/o ports (g0?7). the miw circuit is con?ured using the wakeup enable (wken), wakeup edge (wkedg), wakeup pending (wkpnd) and t0cntrl memory mapped registers. 2 the wken, wkedg and wkpnd are 8-bit registers where each bit corresponds to an i/o port pin (see t able 21 ). all four registers are initialized to 0x00 upon a system reset. the pwmoff output signal may also be programmed as an input of the g6 port miw circuit. interrupts may be triggered if the pwmoff/g6 input miw circuit is enabled and con?ured to trigger its microcontroller hardware interrupt (edgei). bit 6 (pwmint) of the ddelay register, if set to 1, selects the pwmoff signal in place of its g6 input to the miw circuit. software must then enable the miw pwmoff/g6 circuit by setting the wken[6] bit. the wkedg[6] bit must also be cleared to select the rising edge transitions on the pwmoff signal as its wkpnd[6] bit trigger. software may monitor the wkpnd[6] ?g or enable the miw hardware interrupt (edgei) to help detect when the pwmoff signal is triggered. refer to the programmable comparator circuit sections of the datasheet for addition details. 9.1 miw con?uration registers the wakeup enable (wken) register individually enables an i/o port s edge transition to trigger a wakeup/interrupt pending ?g. if the wken register bit is 1, the corresponding i/o port s miw circuitry (de?ed by its bit number) is enabled; other- wise, the port circuitry remains disabled and the pending ?g may not be triggered. the wakeup edge (wkedg) register bits are used to program an enabled i/o port s pending ?g to be triggered from either a rising-/falling-edge transition. if the wkedg register bit is 1, a falling-edge transition of the enabled i/o port will trigger the pending ?g. if zero, a rising-edge transition of the enabled i/o port will trigger the pending ?g. the miw circuit shares a single hardware interrupt (edgei) among all pending ?gs and is enabled by the wakeup interrupt enable (wkinten) bit of the t0cntrl register. 2 the wkinten bit enables hardware interrupts for the miw circuit if set to 1. 3 the wakeup pending (wkpnd) register contains the pending ?gs corresponding to each of the i/o port pins. if a wkpnd register bit is 1, the programmed i/o port edge transition has triggered its pending ?g. if zero, the ?g is not pending and n o transition has occurred from the last pending reset. a pending ?g may only be triggered by enabled i/o ports (if its wken register bit is 1). once a pending ?g is triggered, all ?gs are logically-ored together to trigger a wakeout if in halt/idle mode and/or hardware interrupts (if enabled). if software is to re-enter halt/idle mode, all pending ?gs must be cleared, oth- erwise the command is ignored. since all miw pending ?gs share a single hardware interrupt, software must take care with the handling of the pending ?gs when more than one pending ?g is enabled. as long as a miw pending ?g is set, the hard- w are interrupt will continue to execute software s miw interrupt service routine with highest priority until all pending ?gs a re cleared. 4 upon exiting halt/idle mode or before leaving software s miw interrupt service routine, the rbit instruction may be used to clear a particular pending ?g. the rbit instruction takes two instruction clock cycles to complete its execution. in the ?st c ycle, all eight register bits are automatically read to obtain their most current value. in the second cycle, the bit to be cl eared is given its new value and all bits are then re-written to the register. using the rbit instruction to clear an individual pending ?g causes no potential hazards if only one wakeup i/o port is enabled. however, if more than one i/o port is enabled software may inadvertently clear a recently triggered pending ?g if the trigger happened during the second phase of the rbit instruction ex ecution. to avoid this condition, the ld instruction must be used to clear a set pending ?g. the miw circuit is designed such that software may not trigger a pending ?g by writing a 1 to a wkpnd register bit, it may only be cleared. the action of writing a 1 to a wkpnd register bit holds the current bit value. the action of writing a 0 to a wkpnd register bit clears the b it v alue. therefore, the ?d wkpnd, #0f7h?instruction will clear the wkpnd[3] while all others bits remain the same. fms7401l product specification 45 rev. 1.0.3 1/24/05 the miw circuit can be used with the i/o ports con?ured as both an input and output. the miw con?uration and function is the same for both i/o con?urations. however, when using the miw circuit to wake the device from halt/idle mode the wa k eup i/o port must be con?ured as an input, otherwise the device will never exit the mode. ta b le 22. multi-input wakeup (miw) register bit assignments figure 15. multi-input wakeup (miw) block diagram 6 1. refer to the power saving modes section of the datasheet for detail regarding halt and idle mode. 2. refer to table 30 of the device memory section of the datasheet for the detailed memory map. 3. hardware interrupts are not executed by the microcontroller core unless the global interrupt enable (g) flag of the status re gister is set. refer to the 8-bit microcontroller core section of the datasheet for details. 4. no other hardware interrupts will be executed, aside from the software interrupt instruction, until the miw hardware interrup t is no longer executed. refer to the 8-bit microcontroller core section of the datasheet for details. 5. available only on the 14-pin package option. 6. the pwmoff and pwmint signals are the outputs from the programmable comparator s digital filter circuit. refer to programmable comparator circuit section of the datasheet for details. wken, wkedg, wkpnd registers (addr. 0xb1, 0xaf, 0xb0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 g7 5 pwmoff 6 /g6 5 g5 g4 g3 g2 g1 g0 edgei wakeout data bus 7 0 wken[7:0] 7 0 wkedg[7:0] wkpnd[7:0] g0 wkinten g7 g6 y a b sel pwmoff pwmint product specification fms7401l rev. 1.0.3 1/24/05 46 10 8-bit microcontroller core the fms7401l s 8-bit microcontroller core is speci?ally designed for low cost applications involving bit manipulation, shift- ing and block encryption. it is based on a modi?d harvard architecture meaning peripheral, i/o and ram locations are addressed separately from instruction data. the core differs from the traditional harvard architecture by aligning the data and instruction memory sequentially. this allows the x-pointer (11-bits) to point to any memory location in either segment of the memory map. this modi?ation improves the overall code ef?iency of the microcontroller core and takes advantage of the ?xibility found on the von neu- mann architecture and stored program concept. 10.1 core registers the microcontroller core has ?e general-purpose registers. these registers are the accumulator (a), x-pointer (x), program counter (pc), stack pointer (sp) and status register (sr). the x, sp and sr registers are memory mapped while a and pc are not. figure 16. core program model negative flag global interrupt enable ready flag zero flag carry flag half carry flag 0 7 0 0 0 3 9 10 00 n h c z g r a x pc sp sr 8-bit accumulator register 4-bit stack pointer 8-bit status register 10-bit program counter 11-bit x pointer register fms7401l product specification 47 rev. 1.0.3 1/24/05 10.1.1 accumulator (a) the accumulator is a general-purpose 8-bit register that is used to hold data and results of arithmetic calculations or data manipulations. 10.1.2 x-pointer (x) the x-pointer register allows for an 11-bit indexing value to be added to an 8-bit offset creating an effective address used fo r reading and writing among the memory space. this provides software with the ?xibility of storing lookup tables in the code eeprom memory space for the core s accessibility during normal operation. 1 the microcontroller core allows software to access the entire 11-bit x-pointer register using the special x-pointer instruction s e.g. ld x, #040h (see t able 24 ). software may also access the register through any of the memory mapped instructions using the xhi (x[10:8]) and xlo (x[7:0]) variables located at address 0xbe and 0xbf (see t able 30 ). the x register is divided into two sections. the most signi?ant bit (msb) is write only and selects between the data (0x000 to 0x0ff) or program (0xc00 to 0xfff) memory space. the 10 least signi?ant bits (lsbs) represent the speci? address location within the data or program memory space. f or example: if x[10] = 0, the ld a, [#0,x] instruction will take the data at address x[9:0] from the data memory space (0x000 to 0x0ff) and load it into a. however, if x[10] = 1 the ld a, [#0,x] instruction will take the data at address x[9:0] from the program memory space (0xc00 to 0xfff) and load it into a. the x register can also serve as a counter or temporary storage register. however, this is true only for the 10-lsbs since the msb is dedicated for memory space selection. 10.1.3 program counter (pc) the 10-bit program counter (pc) register contains the address of the next instruction to be executed. after a system reset, pc is initialized to 0xc00 and the microcontroller core begins executing the instruction program residing in the code eeprom memory at the initialized pc value. 10.1.4 stack pointer (sp) the microcontroller core has an automatic program stack with a 4-bit stack pointer. the stack can be initialized to any locatio n between addresses 0x30-0x3f in sram. normally, the stack pointer is initialized by one of the ?st instructions in an applica- tion program. after a reset, the stack pointer is defaulted to 0xf pointing to the top of the stack at address 0x3f. the stack is con?ured as a data structure which decrements from high to low memory. each time a new address is pushed onto the stack, the microcontroller core decrements the stack pointer by two. each time an address is pulled from the stack, th e microcontroller core increments the stack pointer is by two. at any given time, the stack pointer points to the next free locat ion in the stack. when a subroutine is called by a jump-to-subroutine (jsr) instruction, the instruction s address is automatically pushed onto the stack with the least signi?ant byte ?st. when the subroutine is ?ished, a return-from-subroutine (ret) instruction is ex ecuted. the ret instruction pulls the previously stacked return address and loads it into the program counter. instruction ex ecution then continues at the pulled return address. 10.1.5 status register (sr) the 8-bit status register (sr) contains four condition code indicators (c, h, z, and n), a global interrupt (g) mask bit, and t he data eeprom write ready (r) ?g. the condition codes are automatically updated by most instructions (see t able 25 ). all sta- tus register bits except for the global interrupt mask are read only when using direct, indirect, or indexed instructions. the carry and half carry bits may be written by using their special inherent (sc, rc, ldc, rrc and rlc) instructions. software cannot restore sr using the traditional microcontroller methods. refer to the interrupt handling section for additional details. product specification fms7401l rev. 1.0.3 1/24/05 48 carry/borrow (c) the carry ?g is set if the arithmetic logic unit (alu) performs a carry or borrows during an arithmetic operation and by its special inherent instructions?et carry (sc), load carry (ldc) and invert carry (invc). the rotate instructions?otate right/ left through carry (rrc/rlc)?perate with and through the carry bit to facilitate multiple-word shift operations. the rc, sc, invc, ldc and stc (store carry) instructions facilitate direct bit manipulation using the carry ?g. half carry (h) the half carry ?g indicates whether an over?w has taken place on the boundary between the two nibbles in the accumulator. it is primarily used for binary coded decimal (bcd) arithmetic calculation. the rc and sc instructions facilitate direct bit manipulation of the half carry ?g. zero (z) the zero ?g is set if the result of an arithmetic, logic, or data manipulation operation is zero. otherwise, the zero ?g is cleared. negative (n) the result from an arithmetic, logic, or data manipulation operation is negative if the msb is one, therefore setting the negat ive ?g. otherwise, the negative ?g is cleared. global interrupt mask (g) the global interrupt bit (g) is a global mask that disables all maskable interrupt sources. if g is cleared, interrupts can bec ome pending but the operation of the core continues uninterrupted (even if the individual interrupts are enabled). however, if g is set when an interrupt becomes pending the core will be interrupted and execute the appropriate interrupt service routine. after a reset, g is defaulted to zero and can only be set by a software instruction. when an interrupt is recognized, g is auto - matically cleared after the program counter value is stacked and the interrupt vector addressing the interrupt service routine is fetched. once the interrupt is serviced, a return-from-interrupt (reti) instruction is normally executed to restore the program counter to the value before the interrupt occurred. g is the restored to one after the return from interrupt is executed. altho ugh g can be set within an interrupt service routine, ?esting?interrupts in this way should only be done when there is a clear understanding of latency and of the arbitration mechanism. ta b le 23. interrupt priority sequence priority (5 highest, 1 lowest) interrupt 5 software (intr) 4 miw (edgei) 3 timer 0 (tmri0) 2 pwm timer 1 (tmri1) 1 adc (adci) product specification fms7401l rev. 1.0.3 1/24/05 49 10.1.6 interrupt handling when an interrupt is recognized, the current instruction completes its execution. the return address (the current value in the program counter, pc) is pushed onto the stack, the global interrupt (g) mask of the status register (sr) is cleared, and execu- tion continues at the address speci?d by the respective interrupt vector (see t able 30 ). this process takes ?e instruction c ycles to complete. the interrupt vector contains the address of the software s interrupt service routine (isr). initially, the isr may save (if necessary) the status register s contents. software, however, cannot restore sr using the traditional microcontrol - ler methods. just before ending the isr, software may restore the contents of sr by using only the special inherent instruction s (e.g. sc, rc and ldc) or specially de?ed software routines since all sr bits except for g are read only when using direct, indirect, or indexed instructions (e.g. ld , st, rbit or sbit). upon exiting the isr, software must clear the appropriate triggering pending ?g and execute a return-from-interrupt (reti) instruction. the reti instruction pulls the saved return address off the stack in reverse order restoring pc and setting g of sr to one. instruction execution resumes at the restored t he program counter address. the microcontroller core is capable of supporting ?e interrupts. four are maskable through g of the sr and the ?th (software interrupt) is not inhibited by g (see figure 17 ). the execution of the intr instruction generates a software interrupt. once the intr instruction is executed, the microcontroller core will interrupt whether g is set or not. the intr interrupt is executed i n the same manner as the other maskable interrupts where pc is stacked and g is cleared. this means, if g was enabled prior to the software interrupt the reti instruction must be used to return from interrupt in order to restore g to one. however, if g w as not enabled prior to the software interrupt the ret instruction must be used. in the case of simultaneous multiple interrupts, the microcontroller core prioritizes the interrupts. see t able 23 for the interrupt service priority sequence. figure 17. basic interrupt structure g intr pwm t1 t0 miw interrupt p ending flags interrupt enable bits global interrupt enable interrupt interrupt source with priority adc t1en t0int en wkint en aint en t1pnd t0pnd wkpnd apnd product specification fms7401l rev. 1.0.3 1/24/05 50 10.2 addressing modes the microcontroller core has seven instruction addressing modes: inherent, immediate, direct, indirect, indexed, absolute jump and relative jump (see t able 24 ). inherent the inherent addressing mode instructions either have no operand associated or the contents of the operand are already known to the microcontroller core. the microcontroller core then inherently knows how to execute the instruction without needing any additional information provided by additional operands. immediate the immediate addressing mode instructions contain a 3-bit, 2 8-bit or 12-bit 3 immediate ?ld as an operand. immediate addressing is so-named because the value needed to complete the instruction is provided immediately to the core within the instruction code. that is to say, the instruction itself dictates what the data value is to be e.g. stored in a register. direct the direct addressing mode instructions contain an 8-bit address operand that directly points to a location within the data memory space. direct addressing is so-named because the value needed to complete the instruction must be directly accessed by the core from the memory address provided by the instruction code. indirect the indirect addressing mode instructions use the content in xlo, x[7:0], to address a speci? location within the data mem- ory space (0x00 ?0xff). 4 indirect addressing is so-named because the value needed to complete the instruction must be retrieved indirectly by the core from the address provided by the x-pointer. indexed the indexed offset addressing mode instructions add an 8-bit unsigned offset value to the x-pointer yielding a new effective address to select a speci? location anywhere within the memory map (both program and data memory space, 0x000-0xfff). indexed addressing expands the functions of indirect addressing by providing the only means to access the data stored within the program memory space. absolute the absolute jump addressing mode instructions (e.g. jmp and jsr) replace the program counter with the value in the operand ?ld. this allows jumping to any location within the program memory space. 5 relative the opcode instruction ?ld for the relative jump addressing mode instruction, jp, is calculated from the distance to the abso- lute program memory location in the operand addressing the next instruction to be executed. the base opcode for jp is 0xc0 where bit 5 indicates the direction within memory to jump. bits 4 to 0 indicate the number of bytes to jump where the maxi- mum distance is 31 bytes. if bit 5 is zero, the address for the next instruction executed is determined by subtracting the lowe r 5 bits of the opcode (0xc1-0xdf) from the program counter; otherwise, the lower 5 bits of the opcode (0xe0-0xff) are added to the program counter. 6 fms7401l product specification 51 rev. 1.0.3 1/24/05 ta b le 24. instruction addressing modes instruction immediate direct indexed indirect inherent relative absolute adc add and or subc xor a, # a, # a, # a, # a, # a, # a, m a, m a, m a, m a, m a, m a, [#, x] a, [#, x] a, [#, x] a, [#, x] a, [#, x] a, [#, x] a, [x] a, [x] a, [x] a, [x] a, [x] a, [x] clr inc dec m m m a a a x x x ifeq ifgt ifne iflt a, # a, # a, # x, # x, # x, # x, # m, # m, # a, m a, m a, m a, [#, x] a, [#, x] a, [#, x] a, [x] a, [x] a, [x] sc rc ifc ifnc invc ldc stc #, m #, m no-op no-op no-op no-op no-op rlc rrc m m a a ld st a, # x, # m, # a, m a, m m, m a, [#, x] a, [#, x] a, [x] a, [x] nop no-op ifbit ifnbit sbit rbit #, a #, a #, m #, m #, m #, m #, [x] #, [x] #, [x] #, [x] jp jsr jmp ret reti intr [#, x] [#, x] no-op no-op no-op rel. m m product specification fms7401l rev. 1.0.3 1/24/05 52 ta b le 25. instruction cycles and bytes mnemonic operand bytes cycles flags affected adc a, [x] 1 1 c,h,z,n adc a, [#,x] 2 3 c,h,z,n adc a, m 2 2 c,h,z,n adc a, # 2 2 c,h,z,n add a, [x] 1 1 z,n add a, [#,x] 2 3 z,n add a, m 2 2 z,n add a, # 2 2 z,n and a, [x] 1 1 z,n and a, [#,x] 2 3 z,n and a, m 2 2 z,n and a, # 2 2 z,n clr x 1 1 z clr a 1 1 c,h,z,n clr m 2 1 c,h,z,n dec x 1 1 z dec a 1 1 z,n dec m 2 2 z,n ifbit #, a 1 1 none ifbit #, m 2 2 none ifbit #, [x] 1 1 none ifc 1 1 none ifeq a, [#, x] 2 3 none ifeq a, [x] 1 1 none ifeq a, # 2 2 none ifeq a, m 2 2 none ifeq m, # 3 3 none ifeq x, # 3 3 none ifgt a, [#, x] 2 3 none ifgt a, [x] 1 1 none ifgt a, # 2 2 none ifgt a, m 2 2 none ifgt x, # 3 3 none iflt x, # 3 3 none ifnbit #, a 1 1 none ifnbit #, m 2 2 none ifnbit #, [x] 1 1 none ifnc 1 1 none ifne a, [#, x] 2 3 none ifne a, [x] 1 1 none ifne a, # 2 2 none ifne a, m 2 2 none ifne x, # 3 3 none ifne m, # 3 3 none inc a 1 1 z,n inc m 2 2 z,n mnemonic operand bytes cycles flags affected inc x 1 1 z intr 1 5 none invc 1 1 c jmp m 3 4 none jmp [#, x] 2 3 none jp 1 1 none jsr m 3 5 none jsr [#, x] 2 5 none ld a, # 2 2 none ld a, [#,x] 2 3 none ld a, [x] 1 1 none ld a, m 2 2 none ld m, # 3 3 none ld m, m 3 3 none ld x, # 3 3 none ldc #, m 2 2 c nop 1 1 none or a, [x] 1 1 z, n or a, [#,x] 2 3 z,n or a, m 2 2 z,n or a, # 2 2 z,n rbit #, [x] 1 2 z,n rbit #, m 2 2 z,n rc 1 1 c,h ret 1 5 none reti 1 5 none rlc a 1 1 c,z,n rlc m 2 2 c,z,n rrc a 1 1 c,z,n rrc m 2 2 c,z,n sbit #, [x] 1 2 z,n sbit #, m 2 2 z,n sc 1 1 c,h st a, [#,x] 2 3 none st a, [x] 1 1 none st a, m 2 2 none stc #, m 2 2 z,n subc a, [x] 1 1 c,h,z,n subc a, [#,x] 2 3 c,h,z,n subc a, m 2 2 c,h,z,n subc a, # 2 2 c,h,z,n xor a, [x] 1 1 z,n xor a, [#,x] 2 3 z,n xor a, m 2 2 z,n xor a, # 2 2 z,n fms7401l product specification 53 rev. 1.0.3 1/24/05 1. the fms7401l? normal mode operation begins after a system reset and is when the 8-bit microcontroller core begins executing the instruction program residing in the code eeprom memory. during this time, the code eeprom memory may only be read by software not written. refer to the device memory section of the datasheet for additional memory addressing information. 2. a 3-bit value in cases like the ifbit and ifnbit instructions. 3. a 12-bit value in the case of instructions writing to x. 4. the content of xhi (x[10:8]) is ignored. 5. the program memory space for the fms7401l is 0xc00 to 0xfff; however, the program counter will use only the 10 least signific ant bits of the address provided. 6. although the jp instruction can jump forward 31 bytes, it can only jump backwards 30 bytes because the program counter is aut omatically incremented while the jp instruction is being executed. product specification fms7401l rev. 1.0.3 1/24/05 54 11 device memory the fms7401l has 64 bytes of sram and 64 bytes of eeprom (data eeprom) available for data storage. it also has 1k byte of eeprom (code eeprom) memory for program storage. during the device s normal operation, software has both read and write access of sram and data eeprom memories but has only read access of the code eeprom. 1 that is, the code eeprom is pro- tected from unauthorized writes that can corrupt its contents during normal operating conditions. the code eeprom can only be written to when the device is in programming mode 2 and if the write disable (wdis) bit of initialization register 1 is set to 0 while in normal operating mode, the user can write to the data eeprom array by polling the ready (r) ?g of the status register then ex ecuting the appropriate instruction. if the r ?g is 1, the data eeprom block is ready to perform the next write. if the r ? g is 0, the data eeprom is busy performing a write operation. the data eeprom array will set the r ?g to 1 after completing the write operation. attempts to read, write, or enter halt/idle mode while the data eeprom is busy (r=0) can affect the current data bei ng written and cause the intruding read or write command to also fail. the sram, data eeprom, code eeprom, and all other data register are memory mapped for easy access by software (see t able 30 ). the microcontroller core has an 11-bit x-pointer register that may be used to address data bytes within the memory map. 3 bit 10 of the x-pointer (x[10] or xhi[1]) selects between the code and data memory space within the memory map. when x[10] is set to 1, the x-pointer selects the code memory space (addr. 0xc00 to 0xfff) physically addresses a byte in the code eeprom memory. since the code eeprom memory is 1k bytes, it requires only 10 address bits to physically address a byte of its memory. bits 9-0 of the x-pointer (x[9:0] or {xhi[1:0],xlo[7:0]}) is the physical address of the code eeprom used during a byte read instruction operation. when x[10] is set to 0, the x-pointer automatically addresses the data memory space (addr. 0x00 to 0xff). bits 9-0 of the x-pointer is the memory mapped (not physical) address for the entire data memory space (including the sram, data eeprom, and all other data registers) used during a byte read/write instruction operation. in addition, when using x-pointer instructions with the "[x]" syntax, only the lower 8 bits of x are considered addressing the dat a memory space only. however, instructions with the "[#0,x]" syntax allow read access of the code memory space for look-up tables, etc. when using the x-pointer to address a byte in either the data or code memory space, software should load x with its 12-bit memory mapped address. 11.1 initialization registers the fms7401l has four 8-bit wide non-volatile initialization registers that are only accessible by the user in programming mode (if the memory security bits are not enabled). each register has a corresponding shadow volatile register that is automat- ically updated during a reset and is used to initialize speci? on-chip peripherals. the initialization register 1 contains the three memory security bits, three feature enable bits, and the clock selection bit. t able 26 provides a detailed description of the initialization register 1. this register is defaulted to zero by the factory. the initialization register 2 contains the internal oscillator frequency trim setting, f osc . 4 prior to leaving the factory, the inter- nal oscillator is trimmed to the appropriate frequency and the non-volatile register is pre-programmed. during a reset, the vol - atile shadow register (at address 0xba) is updated with the factory programmed trim value. the shadow register associated with the initialization register 2 is accessibly by software during normal operation and may be written to in order to perform ?e adjustments e.g. of the pwm timer outputs. if the software saved the original factory trim value, the software may restore the frequency to its original frequency. 5 the initialization register 3 contains the factory calibration values for the two internal analog comparator circuits (brown-ou t reset and programmable comparator). the calibration is performed in order to con?ure the comparators to their proper lev- els (see t able 27 ). the non-volatile register is preprogrammed prior to leaving the factory. the initialization register 4 contains the factory calibration value for the internal current source generator as well as the default g0/t1hs1 and g5/t1hs2 port con?uration. the factory calibrates the current source generator to ensure that, if enabled, g3 can source i src 4 of current. during the initial clock cycles of the reset sequence, the shadow register is updated con?uring the g0/t1hs1 and g5/t1hs2 i/o ports to their pre-determined initial states. this offers the capability of driving g0/t1hs1 and g5/t1hs2 high within the ?st t dio 4 after the device is powered. the non-volatile register is pre-programmed fms7401l product specification 55 rev. 1.0.3 1/24/05 prior to leaving the factory with the appropriate calibration value and with the ports con?ured as tri-state inputs. in progra m- ming mode, the default port con?uration may be changed; however, be sure to maintain the factory current source calibration v alue since writes to a single register must affect all bits. the initialization registers 1, 2, 3 and 4 can be read from and written to while in programming mode. however, re-trimming the internal oscillator and re-calibrating the analog circuits once the device has left the factory is discouraged and will voi d all device guarantees. ta b le 26. initialization register 1 bit de?itions ta b le 27. initialization register 3 bit de?itions ta b le 28. initialization register 4 bit de?itions initialization register 1 (volatile/non-volatile addr. 0xb9, 0xbb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 clk_adj cmode unused wden boren ubd wdis 6 rdis 6 (7) clkadj when set, the internal clock trimming register (volatile initialization register 2, addr. 0xba) can be accessed by the core in order to modify the internal clock frequency. (6) cmode clock mode select: 0 = internal oscillator, 1 = external oscillator (4) wden if set, the on-chip processor watchdog timer resets are enabled. (3) boren if set, the on-chip brown-out reset comparator circuit is enabled. (2) ubd if set, write access of the upper 32 bytes of the data eeprom (0x60-0x7f) is disabled in both programming and normal mode. 1 , 2 (1) wdis 6 if set, write access of the device memory is permanently disabled while in programming mode. 2 (0) rdis 6 if set, read access of the device memory is permanently disabled while in programming mode. 2 initialization register 3 (volatile/non-volatile addr. 0xd0, 0xd1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused unused bor_trim comp_trim (5:3) bor_trim these three bits allow for the calibration of the brown-out reset comparator circuit. (2:0) comp_trim these three bits allow for the calibration of the programmable comparator? upper range circuit. initialization register 4 (volatile/non-volatile addr. 0xd3, 0xd4) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t1hs_dir t1hs2_lev t1hs1_lev isource_trim[4:0] (7) t1hs_dir initializes during reset, the t1hs1 (g0) and t1hs2 (g5) i/o ports both either inputs or outputs. this bit shadows directly to bits 0 and 5 of portgc. (6:5) t1hsx_lev initializes during reset, the individual t1hs1 (g0) and t1hs2 (g5) i/o port level. these bits shadow directly to bits 0 and 5 of portgd. (4:0) isource_trim these five bits allow for the calibration of internal current source generator. product specification fms7401l rev. 1.0.3 1/24/05 56 ta b le 29. t1hs1 (g0) and t1hs2 (g5) default con?uration t1hs_dir t1hs2_lev t1hs1_lev description 0 0 0 t1hs1 and t1hs2 tri-state inputs 0 0 1 t1hs1 input with pull-up, t1hs2 input tri-state 0 1 0 t1hs1 input tri-state, t1hs2 input with pull-up 0 1 1 t1hs1 and t1hs2 input with pull-up 1 0 0 t1hs1 and t1hs2 push-pull 0 outputs 1 0 1 t1hs1 push-pull 1 output, t1hs2 push-pull 0 output 1 1 0 t1hs1 push-pull 0 output, t1hs2 push-pull 1 output 1 1 1 t1hs1 and t1hs2 push-pull 1 outputs fms7401l product specification 57 rev. 1.0.3 1/24/05 11.2 memory map all i/o ports, peripheral registers, and core registers (except the accumulator and the program counter) are mapped into the memory space. ta b le 30. memory mapped registers address memory space block contents 0x00 ?0x3f data sram data ram 0x40 ?0x7f data eeprom data eeprom 0x9d data adc adata register 7 0x9f data adc adcntrl1 register 0xa0 data adc adcntrl2 register 0xa2 data prog. comparator ddelay register 0xa4 data pwm timer 1 pscale register 0xa5 data pwm timer 1 dtime register 0xa6 data pwm timer 1 t1cmpalo register 0xa7 data pwm timer 1 t1cmpahi register 0xa8 data pwm timer 1 t1cmpblo register 0xa9 data pwm timer 1 t1cmpbhi register 0xaa data pwm timer 1 t1ralo register 0xab data pwm timer 1 t1rahi register 0xac data pwm timer 1 tmr1lo register 7 0xad data pwm timer 1 tmr1hi register 7 0xae data pwm timer 1 t1cntrl register 0xaf data miw wkedg register 0xb0 data miw wkpnd register 0xb1 data miw wken register 0xb2 data i/o portgd register 0xb3 data i/o portgc register 0xb4 data i/o portgp register 7 0xb5 data timer 0 wdsvr 0xb6 data timer 0 t0cntrl register 0xb7 data clock halt mode register 0xb9 data init register initialization register 1 (volatile) 8 0xba data ace core internal clock trimming register (volatile) 0xbb data init register initialization register 1 8 0xbc data init register initialization register 2 8 0xbd data prog. comparator comp register 0xbe data ace core xhi register 0xbf data ace core xlo register 0xc0 data ace core power mode clear (pmc) 0xce data ace core sp register 0xcf data ace core status register (sr) 9 0xd0 data ace core initialization register 3 (volatile) 8 0xd1 data init register initialization register 3 8 0xd2 data signature device_id register 7 0xd3 data init register initialization register 4 (volatile) 8 0xd4 data init register initialization register 4 8 0xc00 ?0xff5 program eeprom code eeprom 0xff6 ?0xff7 program ace core timer0 interrupt vector 0xff8 ?0xff9 program ace core pwm timer1 interrupt vector 0xffa ?0xffb program ace core miw interrupt vector 0xffc ?0xffd program ace core software interrupt vector 0xffe ?0xfff program ace core adc interrupt vector product specification fms7401l rev. 1.0.3 1/24/05 58 ta b le 31. memory mapped registers and their register bit de?itions 1. the fms7401l? normal mode operation begins after a system reset and is when the 8-bit microcontroller core begins executing the instruction program residing in the code eeprom memory. 2. the fms7401l must be placed in a special programming mode of operation in order to have full write and read access of all of the device memories. refer to the in-circuit programming specification section of the datasheet for details. 3. refer to the the 8-bit microcontroller core section of the datasheet for additional details. 4. refer to the electrical characteristics section of the datasheet. 5. the initialization register 2 shadow register will automatically be restored with its original factory setting during a syste m reset. 6. once the read and/or write protection is enabled, the only possible external action of accessing the memory in programming mo de is to issue a ?rogram erase command through the programming interface that clears the entire code eeprom memory contents including the volatile initializat ion register 1. this allows full access to the user enabling new device memory programming for the single programming mode session (unless the non-volatile wdis and rdis bits are cleared). refer to the in-circuit programming specification section of the datasheet for addition details. 7. the register can only be read. 8. the register cannot be access during normal operation only in programming mode. 9. all sr bits except for bit 7 (the global interrupt mask) are read only when using direct, indirect, or indexed instructions. software cannot restore sr using the tradi- tional microcontroller methods. refer to the 8-bit microcontroller core section of the datasheet for additional details. 10.a) names in all capital letters are predefined in the assembler. b) names of the individual bits are not predefined and must be definced using an equ statement in the user program source code: for example, ?pnd equ 7? c) the initialization registers listed are the non-volatil e registers. each register has a volatile shadow register. de?itions of register bits address name 10 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x9d adata 8-bit digital value of adc conversion 0x9f adcntrl1 apnd ainten astart refsel achsel [3:0] 0xa0 adcntrl2 refby2 compsel enamp endas aspeed [1:0] enis gain 0xa2 ddelay compen pwint epwm offmode dd [3:0] 0xa4 pscale pllen fs [1:0] fsel fmode ps [2:0] 0xa5 dtime x x x dt [4:0] 0xa6 t1cmpalo low 8 bits of 12-bit t1cmpa register 0xa7 t1cmpahi x x x x high 4 bits of 12-bit t1cmpa register 0xa8 t1cmpblo low 8 bits of 12-bit t1cmpb register 0xa9 t1cmpbhi x x x x high 4 bits of 12-bit t1cmpb register 0xaa t1ralo low 8 bits of 12-bit t1ra register 0xab t1rahi x x x x high 4 bits of 12-bit t1ra register 0xac tmr1lo low 8 bits of 12-bit tmr1 register 0xad tmr1hi x x x x high 4 bits of 12-bit tmr1 register 0xae t1cntrl t1c3 t1c2 t1c1 t1c0 t1pnd t1en x t1bout 0xaf wkedg bit number = port number, edge direction 0xb0 wkpnd bit number = port number, pending flag for port 0xb1 wken bit number = port number, interrupt enable for port 0xb2 portgd bit number = port number, data when output, weak pull-up when input 0xb3 portgc bit number = port number, input or output setting of port 0xb4 portgp bit number = port number, digital value at pin, read-only 0xb5 wdsvr accepts the value 0x1b as a watchdog service 0xb6 t0cntrl wkinten x x x x x t0pnd t0inten 0xb7 halt reserved reserved reserved reserved reserved reserved eidle ehalt 0xbb initreg1 clk_adj cmode unused wden boren ubd wdis rdis 0xbc initreg2 8-bit value used internally to trim the internal oscillator frequency 0xbd comp cl [5:0] vloop cout 0xbe xhi x x x x x code/data x [9:8] 0xbf xlo low 8 bits of 11-bit x register 0xce sp x x x x sp [3:0] 0xcf status ee ready unused unused global int. zero carry half carry negative 0xd1 initreg3 unused unused bor_trim [2:0] comp_trim [2:0] 0xd4 initreg4 t1hs_dir t1hs2_lev t1hs1_lev isource_trim [4:0] fms7401l product specification 59 rev. 1.0.3 1/24/05 12 in-circuit programming speci?ation the fms7401l supports in-circuit programming of all internal memory mapped registers including the data eeprom, code eeprom, and initialization registers. in-circuit programming consists of a 4-wire serial interface used to place the device in pro- gramming mode and issue all programming commands. 1 the external programmer should follow the device pinout 1 de?ed in fig- ure 18 and the timing rules de?ed by the parameters listed in t able 31 as shown in figure 19 and figure 20 . figure 18. programming mode pin configurations ta b le 32. programming interface electrical characteristics 2 12.1 programming mode interface in order to place the device in programming mode, a 10-bit opcode (0x34b) must be shifted into the device during its system reset. a system reset may be triggered during the device power-up by the power-on reset circuit or with the device already powered with a low pulse on the device reset pin. 3 after power-up, the external programmer must shift in the 10-bit opcode before the system reset sequence completes. if the correct opcode is shifted, the device will automatically enter programming mode once the system reset sequence has completed. the 10-bit opcode is serially shifted with the most signi?ant bit (msb) ?st into the device through the shift_in pin. each opcode data bit must be valid by t dis before the rising edge of clock. as the opcode is shifted, the current 10-bit pattern is compared against 0x34b. if the 10-bit pattern is a match, the device will set the program mode ?g and the device will enter programming mode once the system reset sequence completes (see figure 19 ). symbol parameter conditions min. typ. max. units t hi clock high time 25 ? 500 dc ns t lo clock low time 25 ? 500 dc ns t dis shift_in setup time 25 ? 100 ns t dih shift_in hold time 25 ? 100 ns t dos shift_out setup time 25 ? 100 ns t doh shift_out hold time 25 ? 900 ns t a ccess shift_out sample time 25 ? 500 dc ns t load1 , t load2 , t load3 , t load4 loading time 25 ? 5 ? t ready eeprom write time 25 ? 3.7 ms t reset system reset time 25 ? 3.7 ms shift_in load clock shift_out nc/vcc gnd vcc nc 1 2 6 7 8 3 4 5 nc/vcc shift_out gnd shift_in load vcc nc clock 1 2 6 7 8 3 4 5 fms7401l 8-pin pdip/soic fms7401l 8-pin tssop fms7401l 14-pin pdip/soic/tssop shift_in load nc clock shift_out nc gnd nc vcc nc/vcc nc/vcc nc reset 1 2 6 78 9 13 14 3 411 12 510 nc/gnd product specification fms7401l rev. 1.0.3 1/24/05 60 the opcode must be shifted in after vcc settles to its nominal voltage level and before the system reset sequence (t reset ) com- pletes. otherwise, the device will begin with its normal operation executing the instruction program residing in the code eeprom memory. if an external reset is applied by bringing the reset pin low, the 10-bit opcode may be shifted once reset is released and before the system reset sequence completes. 12.2 programming protocol once the device is in programming mode, the programming protocol and commands may be issued. an externally controlled 4-wire interface consisting of a load (g3) control, serial data shift_in (g4) input, serial data shift_out (g2) output, and clock (g1) pins are used to access the internal memory and registers. communication between the external programmer and the fms7401l is performed through a 32-bit command and response word, as described in t able 23 . the serial data tim- ing for the 4-wire interface is shown in figure 20 and the programming protocol is shown in figure 19 . in order to exit pro- gramming mode, the device must be powered down or an external reset must be applied. 12.2.1 byte write sequence after the external programmer puts the fms7401l into programming mode, the load pin must be set to vcc before serially shifting the ?st 32-bit command word using the shift_in and clock signals. by de?ition, bit 31 of the command word must be shifted ?st followed by all other bits. with each bit of the 32-bit write command word shifted, the device shifts out a bit of the 32-bit response word from the previous command through the shift_out pin. the external programmer may sam- ple shift_out after t a ccess from the rising edge of clock. the serial response word sent immediately after entering pro- gramming mode may contain indeterminate data. after all 32 bits of the command word are shifted, the external programmer must set the load signal to 0v and apply two clock pulses to the clock signal, as shown in figure 19 , to complete the program cycle. once the load signal is brought low, the shift_out pin acts as the handshaking signal between the device and external programmer hardware. when execut- ing the write command, the device sets shift_out low by the time the external programmer has issued the second rising edge of clock informing the external programmer that the memory write is in progress. the external programmer must wait t ready for shift_out to return high before returning the load signal to vcc to initiate the next command cycle. 12.2.2 page write sequence p age mode is a convenient and fast way to program the code eeprom memory. in this mode, 16 bytes of data are written using a single write command followed by a stream of data bytes. only full pages can be written in page mode where the address in the command word points to the beginning of a page. 4 after all 16 bytes of data has been shifted, the data will be written at once speeding up the total write time by a factor of 16 compared to byte mode programming. figure 21 shows the page mode programming protocol. p age mode s 32-bit write command word is similar to a byte write command except that bit 31 must be set to 1 in order to enable page mode. the address in the page-write command word (bits 17 to 8) must select the page to program the 16 bytes of data (the page address is a multiple of the page size: 0x000, 0x010, 0x020, etc.). the ?st byte of the page to program must be placed in the last 8 bits of the page-write command word (bits 7 to 0). all other bytes in the page must immediately follow aft er the initial page-write command has been entered. the load pin must be set to vcc before serially shifting in the 32-bit page-write command word using the shift_in and clock signals. by de?ition, bit 31 of the command word must be shifted ?st followed by all other bits. after all 32 bits of the command word are shifted, the external programmer must set the load signal to 0v and apply two clock pulses to the clock signal to latch the ?st byte of the page in its temporary data buffer. the load signal must be returned to vcc in order for the external programmer to shift the second byte of the page into the device (without repeating the command word). once all 8 bits of the byte are shifted, the load signal must again be set to 0v followed by two clocks pulses of the clock signal in order to latch byte into its temporary data buffer. this process must be repeated until all 16 bytes are loaded into their data buffers. while the 16 th byte of data is being latched, the actual write to the code eeprom page, selected by the address in the 32-bit page-write command word, occurs. once the load signal is brought low, the shift_out pin acts as the handshaking signal fms7401l product specification 61 rev. 1.0.3 1/24/05 between the device and external programmer hardware. the device sets shift_out low during a page-write command by the time the external programmer has issued the second rising edge of clock informing the programmer that the memory write is in progress. the external programmer must wait t ready for shift_out to return high before returning the load signal to vcc to initiate the next command cycle. 12.2.3 byte read sequence the external programmer can only perform memory reads a byte at a time. before shifting each new command, the external programmer must set the load signal to vcc. by de?ition, bit 31 of the command word must be shifted ?st followed by all other bits. with each bit of the 32-bit read command word shifted, the device shifts out a bit of the 32-bit response word from the previous command through the shift_out pin. the external programmer must sample shift_out after t a ccess from the rising edge of clock. the serial response word sent immediately after entering programming mode may contain indeter- minate data. after all 32 bits of the read command word are shifted, the external programmer must set the load signal to 0v and apply two clock pulses to the clock signal, as shown in figure 19 , to complete the read cycle. at the rising edge of the second clock pulse, the data read from the address provided in the read command word is latched into the lower 8-bits of its response w ord. once load is returned to vcc, the next 32-bit command word may be shifted while the response word to the previous read command is shifted out with the data read from memory. if the last read command has been shifted, a dummy read com- mand must be shifted to collect the last response word containing the last data byte read. ta b le 33. 32-bit command and response word bit number input command word output response word bit 31 set to 1 to enable page mode memory access otherwise 0 for byte mode. same as the input command word. bit 30 must be set to 0. same as the input command word. bit 29 set to 1 to access the data memory space (data eeprom or initialization registers) otherwise 0. same as the input command word. bit 28 set to 1 to access the code eeprom otherwise 0. same as the input command word. bits 27 ?25 must be set to 0. same as the input command word. bit 24 set to 1 to perform a read or 0 to perform a write. same as the input command word. bit 22 set to 1 to perform a program memory erase otherwise 0. same as the input command word. bits 23, 21 ?18 must be set to 0. same as the input command word. bits 17 ?8 lower 10-bits of the memory mapped address byte to read/write or first byte of the page to write. same as the input command word. bits 7 ?0 data to be programmed if a write command or all zeros if a read command. same as the previous input write command word or the data read after an input read command word. product specification fms7401l rev. 1.0.3 1/24/05 62 figure 19. programming protocol figure 20. serial data timing 1 figure 21. page mode protocol vcc load (g3) c lo c k (g 1 ) s hift_in (g 4 ) shift_ o u t (g 2 ) ( in write mode ) b it 3 1 b it 3 0 b it 0 b it 3 1 shift_ o u t (g 2 ) ( in re a d mode ) a : s t a rt o f p ro g r a mmin g cycl e 3 2 cl o c k p u ls e s t load 2 b u s y re ad y a t load 4 t load3 t re ad y b u s y l ow b y 2 nd cl o c k p u ls e t load 1 11 1 1 11 000 0 1 0 - b it o pc ode = 0 x 3 4 b t re s e t a re s e t v alid v alid shift_out (g2) shift_in (g4) clock (g1) t hi t lo t dis t dih t doh t dos 0x90 pag ewr 0x00 0x00 p age 0 byte 1 (first) 32 clock cycles 8 clock cycles 8 clock cycles p age 0 byte 2 p age 0 byte 3 continue with next bytes in the page 8 clock cycles p age 0 byte 16 (last) page 1 byte 1 (first) 32 clock cycles 0x90 p agewr 0x00 0x10 32-bit command = page write from address 0xc00 32-bit command = page write from address 0xc10 check ready/busy page write ready load shift_in clock shift_out fms7401l product specification 63 rev. 1.0.3 1/24/05 12.2.4 program memory erase the external programmer may erase the entire code eeprom memory array using two special program erase byte write commands. this special erase option may also be used to unlock memory protected (wdis/rdis=1) devices without compromising design secu- rity. the special program erase byte write command overrides the wdis memory security bit if set. once both special byte write commands are issued, the volatile initialization register 1 is automatically cleared to unprotect the current programming mode session and allow complete access of the device memories. 5 the external programmer may then re-program the code eeprom with a new pattern or permanently disable all security features by re-programming the non-volatile initialization register 1. all ot her memories, including the data eeprom, are unaffected by the program erase commands. the special program erase protocol requires the external programmer to shift two 32-bit command words addressing two separate page addresses. the special program erase 32-bit command word is similar to a byte write command except that bit 22 must be set to 1 to enable the program erase mode. the code eeprom memory must also be selected by setting bit 28 of the command word. the ?st command word must select all even pages of the memory by setting the address bits (bits 17 to 8) to 0x000. the second command word must select all odd pages by setting the address bits to 0x010 of the command word. any data value (bits 7 to 0) shifted as part of the individual command word may be used to erase the pages of the code eeprom. after each even/odd page program erase command is executed, the even/odd pages of the code eeprom memory is ?led with the data supplied in the command erasing their previous program code data values. if the external programmer issues only one of the (even/odd page) erase commands, only half the pages will be erased by the data selected and the volatile initialization register 1 will not be cleared. therefore, the current programming mode session will remain protected if either the memory protection (wdis/rdis) bits are set. after the external programmer puts the fms7401l into programming mode, the load pin must be set to vcc before serially shifting the ?st 32-bit program erase command word using the shift_in and clock signals. by de?ition, bit 31 of the command word must be shifted ?st and then followed by all other bits. with each bit of the 32-bit write command word shifted, the device shifts out a bit of the 32-bit response word from the previous command through the shift_out pin. the e xternal programmer may sample shift_out after t a ccess from the rising edge of clock. the serial response word sent immediately after entering programming mode may contain indeterminate data. after all 32 bits of the command word are shifted, the external programmer must set the load signal to 0v and apply two clock pulses to the clock signal, as shown in figure 19 , to complete the program cycle. once the load signal is brought low, the shift_out pin acts as the handshak- ing signal between the device and external programmer hardware. when executing the write command, the device sets shift_out low by the time the external programmer has issued the second rising edge of clock informing the external programmer that the memory write is in progress. the external programmer must wait t ready for shift_out to return high before returning the load signal to vcc to initiate the second program erase command cycle. the volatile initialization register 1 will only be cleared if both commands are successfully executed. all other memory accesses from this point forward are executed normally. 1. during in-circuit programming, g5 must be either not connected or driven high. 2. the following characteristics are guaranteed by design but are not 100% tested. 3. for addition detail regarding the device power-up and reset conditions refer the reset circuit section of the datasheet. 4. each page in the code eeprom has 16 bytes and starts at address 0xc00, 0xc10, 0xc20, etc. 5. for additional details regarding the wdis, rdis, and initialization registers, refer to the device memory section of the datasheet. product specification fms7401l rev. 1.0.3 1/24/05 64 13 electrical characteristics absolute maximum ratings operating conditions p arameter min. typ. max. unit ambient storage temperature -65 +150 ? input voltage -0.3 vcc + 0.3 v vcc input voltage 4.0 v lead temperature (10s max) +300 ? electrostatic discharge on all pins 2000 v internal voltage regulator output current 5 ma relative humidity (non-condensing) 95% eeprom write limits see ac electrical characteristics fms7401l product specification 65 rev. 1.0.3 1/24/05 13.1 fms7401l (2.7v to 3.6v) dc electrical characteristics all measurements are valid for t a =+25? unless otherwise stated. symbol parameter conditions min. typ. max. units i cc 1 active supply current (without data eeprom writes in progress) f iclk =f osc 2 -40? to 125? 0.75 1.2 ma active supply current (with data eeprom writes in progress) f iclk =f osc 2 -40? to 125? 0.9 2.0 ma active supply current (without data eeprom writes in progress) f iclk =f (fs=0) 2 -40? to 125? 6.5 13 ma i str 3 start-up current 250 ? i cch halt mode current -40? to 85? 1.3 5 a -40? to 125? 8.3 15 ? i ccl 4 idle mode current -40? to 125? 180 270 ? s vcc 3 power supply ramp rate 1v/10ms 1v/1? v il input low with schmitt trigger buffer -40? to 125? 0.2vcc v v ih input high with schmitt trigger buffer -40? to 125? 0.8vcc v i tl tri-state leakage -40? to 125? 0.01 1 ? i ip input pull-up current v in =0v 85 350 ? v ol output low voltage (g1, g2, g3, g4, g6, g7) 5ma sink current -40? to 125? 0.3vcc v output low voltage (g0, g5) 2ma sink current -40? to 125? 0.3vcc v v oh output low voltage (g1, g2, g3, g4, g6, g7) 5ma source current -40? to 125? 0.7vcc v output low voltage (g0, g5) 2ma source current -40? to 125? 0.7vcc v product specification fms7401l rev. 1.0.3 1/24/05 66 ac electrical characteristics all measurements are valid for t a =+25? unless otherwise stated. brown-out reset (bor) electrical characteristics all measurements are valid for t a =+25? unless otherwise stated. programmable comparator electrical characteristics all measurements are valid for t a =+25? unless otherwise stated. symbol parameter conditions min. typ. max. units f osc 5 internal oscillator frequency (factory trim set-point) vcc=3.3v 1.96 2.00 2.04 mhz ? ckv internal oscillator frequency voltage variation -0.5 +0.5 % ? ckt internal oscillator frequency temperature variation vcc=3.3v -40? to 85? -3 +3 % vcc=3.3v -40? to 125? -4 +4 % f pll pll input reference frequency 2.00 mhz t pll_lock 3 pll lock time -40? to 125? 60 ? t eew eeprom writing time 3.7 5 ms t reset 3 system reset time -40? to 125? 2.5 3.7 4.7 ms t dio 3 t1hs1 and t1hs2 default i/o configuration settling time 40 ? t halt_rec 3 internal device start time after exiting from halt where f iclk = f osc 2 -40? to 125? 5 7 ? p arameter conditions min. typ. max. units bor trigger vcc threshold level 2.64 2.71 2.78 v -40? to +85? 2.60 2.83 v -40? to 125? 2.59 2.83 v p arameter conditions min. typ. max. units all 32 thresholds (v thu ) -6% v thu +6% v upper range (0.45v to 2.0v) -40? to 125? -8% v thu +8% v all 31 thresholds (v thl ) v thu ?30mv v thl v thu + 30mv v lower range (0.03v to 0.43v) -40? to 125? v thu ?35mv v thl v thu + 35mv v comparator response time 3 2mv overdrive 359 ns 5mv overdrive 173 ns 10mv overdrive 95 ns fms7401l product specification 67 rev. 1.0.3 1/24/05 adc electrical characteristics all measurements are valid for t a =+25? unless otherwise stated. independent ampli?r electrical characteristics 3 p arameter conditions min. typ. max. units adc integral non linearity (inl) best fit 3 v aref =vcc aspeed=0 where (f iclk =f osc )/1 2 1.5 lsb v aref =internal reference (v ref ) aspeed=0 where (f iclk =f osc )/1 2 1.5 lsb v aref =internal reference (v ref ) aspeed=2 where (f iclk =f osc )/4 2 -40? to +125? 0.5 lsb adc differential non linearity (dnl) 3 vref=vcc aspeed=0 where (f iclk =f osc )/1 2 2.5 lsb v aref =internal reference (v ref ) aspeed=0 where (f iclk =f osc )/1 2 1.5 lsb v aref =internal reference (v ref ) aspeed=2 where (f iclk =f osc )/4 2 -40? to +125? 1 lsb adc conversion time 3 aspeed=0 where (f iclk =f osc )/1 2 -40? to +125? 20 ? internal voltage reference (v ref ) 3 1.215 v amplifier x16 gain error 3 -40? to +125? 2 2 % current source (i src ) on g3/ain1 0.9 1 1.1 ma current source (i src ) on g3/ain1 -40? to +125? 0.89 1 1.11 ma p arameter conditions min. typ. max. units input bias current -40? to +125? -1 +1 ? input offset voltage -40? to +125? 4 mv open loop voltage gain -40? to +125? 97 db gain bandwidth product -40? to +125? 3.7 mhz sink/source current -40? to +125? 0.5 4.5 ma product specification fms7401l rev. 1.0.3 1/24/05 68 figure 22. internal oscillator frequency (f osc ) vs. temperature figure 23. icc active vs. temperature (no pll or data eeprom writes) internal oscillator frequency (f osc ) vs . temperature 1.990 1.992 1.994 1.996 1.998 2.000 2.002 2.004 -40 0 25 85 125 frequency (mhz) 3.6v 3.3v 2.7v temper ature ( c) icc active vs. temperature (no pll or data eeprom writes) 600 650 700 750 800 850 900 -40 0 25 85 125 temper ature ( c) current ( a) 3.6v 3.3v 2.7v fms7401l product specification 69 rev. 1.0.3 1/24/05 figure 24. icc active vs. temperature (no pll, with data eeprom writes) figure 25. icc active vs. temperature (with pll, no data eeprom writes) i cc active vs. temperature (no pll, with data eeprom writes) 700 750 800 850 900 950 1000 1050 1100 -40 0 25 85 125 temperat ure ( c) current ( a) 3.6v 3.3v 2.7v temperat ure ( c) icc active vs. temperature (with pll, no data eeprom write) 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 -40 0 25 85 125 current (ma) 3.6v 3.3v 2.7v product specification fms7401l rev. 1.0.3 1/24/05 70 figure 26. halt current vs. temperature figure 27. idle current vs. temperature (no pll) halt current vs. temperature 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -40 0 25 85 125 current ( a) 3.6v 3.3v 2.7v temper ature ( c) id le current vs. temperature (no pll) 150 160 170 180 190 200 210 -40 0 25 85 125 temper ature ( c) curren t ( a) 3.6v 3.3v 2.7v fms7401l product specification 71 rev. 1.0.3 1/24/05 figure 28. idle current vs. temperature (with pll) figure 29. v ol vs. i ol @ 25? (g1?4, g6, g7) idle current vs. temperature (w ith pll) 1.20 1.30 1.40 1.50 1.60 1.70 -40 0 25 85 125 temper ature ( c) current (ma) 3.6v 3.3v 2.7v v ol vs. i ol @ 25 c (g1-g4, g6, g7) 0.0 0.5 1.0 1.5 2.0 2.5 25 7 10 15 i ol (ma) v ol (v) 3.6v 3.3v 2.7v product specification fms7401l rev. 1.0.3 1/24/05 72 figure 30. v ol vs. i ol @ 25? (g0, g5) figure 31. v oh vs. i oh @ 25? (g1?4, g6, g7) v ol vs. i ol @ 25 c (g0, g5) 0.0 0.5 1.0 1.5 2.0 2.5 25710 15 i ol (ma) v ol (v) 3.6v 3.3v 2.7v v oh vs. i oh @ 25 c (g1-g4, g6, g7) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 25 7 10 15 i oh (ma) v oh (v) 3.6v 3.3v 2.7v fms7401l product specification 73 rev. 1.0.3 1/24/05 figure 32. v oh vs. i oh @ 25? (g0, g5) figure 33. bor level vs. temperature v oh vs. i oh @ 25 c (g0, g5) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 25 7 10 15 i oh (ma) v oh (v) 3.6v 3.3v 2.7v br own-out reset level vs. temperature 2.70 2.71 2.71 2.72 2.72 2.73 2.73 2.74 2.74 2.75 -40 0 25 85 125 temperat ure ( c) voltage (v) bor level product specification fms7401l rev. 1.0.3 1/24/05 74 figure 34. programmable comparator voltage level vs. temperature figure 35. v ref vs. temperature p rogrammable comparator voltage level vs. temperature 0.0 0.5 1.0 1.5 2.0 2.5 -40 0 25 85 125 temper ature ( c) voltage (v) level 1 level 31 level 47 level 63 temper ature ( c) v ref vs. temperature 1.202 1.204 1.206 1.208 1.21 1.212 1.214 1.216 1.218 1.22 1.222 -40 0 25 85 125 voltage (v) 3.6v 3.3v 2.7v fms7401l product specification 75 rev. 1.0.3 1/24/05 figure 36. current source (i src ) vs. temperature figure 37. gain 16 error vs. temperature current source (i scr ) vs. temperature 940 950 960 970 980 990 1000 1010 1020 1030 1040 -40 0 25 85 125 tem perature ( c) current ( a) 3.6v 3.3v 2.7v gain 16 error vs. temperature -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 -40 0 25 85 125 te mperature ( c) percentage ( %) 3.6v 3.3v 2.7v product specification fms7401l rev. 1.0.3 1/24/05 76 1. i cc active current is dependent on the program code and number of active circuits. the i cc active current speci?d is measured with the microcontroller core, pwm timer 1, timer 0, adc, uncommitted ampli?r, and programmable comparator circuits all active. 2. refer to the clock circuit section of the datasheet for details regarding the fms7401l s main system instruction clock (f iclk ) and its clock sources (f osc or f (fs=0) ). 3. the parameter is guaranteed by design but is not 100% tested. 4. the i cc idle current is based on a continuous idle mode looping program and is dependent on the program code. 5. the upper f osc frequency (4mhz) device option is available upon request. fms7401l product specification 77 rev. 1.0.3 1/24/05 ordering information fsid package supply voltage temperature range pa ck a ging option method qty fms7401len pdip8 2.7v to 3.6v -40? to 85? rail 40 fms7401lvn pdip8 2.7v to 3.6v -40? to 125? rail 40 fms7401len14 pdip14 2.7v to 3.6v -40? to 85? rail 25 FMS7401LVN14 pdip14 2.7v to 3.6v -40? to 125? rail 25 fms7401lem8x soic8 2.7v to 3.6v -40? to 85? tape reel 2500 fms7401lemx soic14 2.7v to 3.6v -40? to 85? tape reel 2500 fms7401lemt8x tssop8 2.7v to 3.6v -40? to 85? tape reel 2500 fms7401lemtx tssop14 2.7v to 3.6v -40? to 85? tape reel 2500 product specification fms7401l rev. 1.0.3 1/24/05 78 physical dimensions ?? 8-pin pdip 14-pin pdip ??dimensions are in inches (millimeters) unless otherwise noted. 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident 14 13 12 123 14 13 12 0.740 ?0.770 (18.80 ?19.56) 11 10 9 8 1234567 0.145 ?0.200 (3.683 ?5.080) 0.125 ?0.150 (3.175 ?3.810) 0.014 ?0.023 (0.355 ?0.584) 0.135 0.005 (3.429 0.127) 0.300 ?0.320 (7.620 ?8.128) 0.008 ?0.016 (0.203 ?0.406) 0.250 ?0.010 (6.350 ?0.254) 0.090 (2.286) 0.060 (1.524) 0.092 (2.337) 0.280 (7.112) min 0.065 (1.651) 0.020 (0.508) min 0.030 (0.762) dia max depth 4 typ optional 90 4 typ 95 5 option 1 typ 0.325 8.255 ty p typ 0.050 0.010 (1.270 ?0.254) 0.075 0.015 (1.905 0.381) +0.040 ?.015 +1.016 ?.381 typ 0.100 0.010 (2.540 0.254) typ option 02 pin no. 1 ident pin no. 1 ident index area product specification fms7401l rev. 1.0.3 1/24/05 79 physical dimensions ?? 8-pin soic 14-pin soic ??dimensions are in inches (millimeters) unless otherwise noted. 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8?max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.004 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 123 4567 14 13 12 11 10 9 8 0.335 - 0.344 (8.509 - 8.788) 0.228 - 0.244 (5.791 - 6.198) 0.010 (0.254) max. lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ typ 0.008 (0.203) 0.014 (0.356) 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.008 - 0.010 (0.203 - 0.254) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 30 typ. fms7401l product specification 80 rev. 1.0.3 1/24/05 physical dimensions ?? 8-pin tssop 14-pin tssop ??dimensions are in inches (millimeters) unless otherwise noted. 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0118 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0-8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x 5.0 ?.1 3.2 6.4 17 14 8 4.4 ?0.1 (7.72) typ (4.16) typ (1.78) typ (0.42) typ 0.2 c b a (0.65) typ 0.10 ?0.05 typ all lead tips 0.65 typ. 1.1 max typ 0.19 - 0.30 typ pin #1 ident 0.9 - 0.20 typ (0.9) 0?8 0.6 ?.1 0.25 seating plane gage plane see detail a dimensions are in millimeters notes: unless otherwise specified 1. reference jeded registration mo153. variation ab. ref. note 6, dated 7/93 land pattern recommendation detail a typ. scale: 40x - a - - b - - c - 0.13 c s b a s m 0.1 c all lead tips fms7401l product specification 1/24/05 0.0m 005 stock#ds30007401 ? 2004 fairchild semiconductor corporation life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. |
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